參數(shù)資料
型號(hào): XPC850SRCZT80B
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: Communications Controller Hardware Specifications
中文描述: 32-BIT, 80 MHz, RISC PROCESSOR, PBGA256
封裝: PLASTIC, BGA-256
文件頁數(shù): 65/76頁
文件大?。?/td> 403K
代理商: XPC850SRCZT80B
MOTOROLA
MPC850 (Rev. A/B/C) Hardware Specifications
65
I2C AC Electrical Specifications
Table 8-25 provides the I
2
C (SCL > 100 KHz) timings.
Table 8-25. I
2
C Timing (SCL > 100 KH
Z
)
208
Data setup time
250.00
ns
209
SDL/SCL rise time
1.00
μ
s
210
SDL/SCL fall time
300.00
ns
211
Stop condition setup time
4.70
μ
s
1
SCL frequency is given by SCL = BRGCLK_frequency / ((BRG register + 3) * pre_scaler * 2).
The ratio SyncClk/(BRGCLK/pre_scaler) must be greater or equal to 4/1.
Num
Characteristic
Expression
All Frequencies
Unit
Min
Max
200
SCL clock frequency (slave)
fSCL
0
BRGCLK/48
Hz
200
SCL clock frequency (master)
1
1
SCL frequency is given by SCL = BrgClk_frequency / ((BRG register + 3) * pre_scaler * 2).
The ratio SyncClk/(Brg_Clk/pre_scaler) must be greater or equal to 4/1.
fSCL
BRGCLK/16512
BRGCLK/48
Hz
202
Bus free time between transmissions
1/(2.2 * fSCL)
s
203
Low period of SCL
1/(2.2 * fSCL)
s
204
High period of SCL
1/(2.2 * fSCL)
s
205
Start condition setup time
1/(2.2 * fSCL)
s
206
Start condition hold time
1/(2.2 * fSCL)
s
207
Data hold time
0
s
208
Data setup time
1/(40 * fSCL)
s
209
SDL/SCL rise time
1/(10 * fSCL)
s
210
SDL/SCL fall time
1/(33 * fSCL)
s
211
Stop condition setup time
1/2(2.2 * fSCL)
s
Table 8-24. I
2
C Timing (SCL < 100 KH
Z
) (
CONTINUED
)
Num
Characteristic
All Frequencies
Unit
Min
Max
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