參數(shù)資料
型號(hào): XPC850DECZT66B
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: Communications Controller Hardware Specifications
中文描述: 32-BIT, 66 MHz, RISC PROCESSOR, PBGA256
封裝: PLASTIC, BGA-256
文件頁(yè)數(shù): 6/68頁(yè)
文件大?。?/td> 384K
代理商: XPC850DECZT66B
6
MPC850 (Rev. A/B/C) Hardware Specifications
MOTOROLA
— Supports either transparent or HDLC protocols for each channel
— Independent TxBDs/Rx and event/interrupt reporting for each channel
One universal serial bus controller (USB)
— Supports host controller and slave modes at 1.5 Mbps and 12 Mbps
Two serial management controllers (SMCs)
— UART
— Transparent
— General circuit interface (GCI) controller
— Can be connected to the time-division-multiplexed (TDM) channel
One serial peripheral interface (SPI)
— Supports master and slave modes
— Supports multimaster operation on the same bus
One I
C
(interprocessor-integrated circuit) port
— Supports master and slave modes
— Supports multimaster environment
Time slot assigner
— Allows SCCs and SMCs to run in multiplexed operation
— Supports T1, CEPT, PCM highway, ISDN basic rate, ISDN primary rate, user-defined
— 1- or 8-bit resolution
— Allows independent transmit and receive routing, frame syncs, clocking
— Allows dynamic changes
— Can be internally connected to four serial channels (two SCCs and two SMCs)
Low-power support
— Full high: all units fully powered at high clock frequency
— Full low: all units fully powered at low clock frequency
— Doze: core functional units disabled except time base, decrementer, PLL, memory controller,
real-time clock, and CPM in low-power standby
— Sleep: all units disabled except real-time clock and periodic interrupt timer. PLL is active for
fast wake-up
— Deep sleep: all units disabled including PLL, except the real-time clock and periodic interrupt
timer
— Low-power stop: to provide lower power dissipation
— Separate power supply input to operate internal logic at 2.2 V when operating at or below
25 MHz
— Can be dynamically shifted between high frequency (3.3 V internal) and low frequency (2.2 V
internal) operation
Debug interface
— Eight comparators: four operate on instruction address, two operate on data address, and two
operate on data
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