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| 型號(hào)： | XCS05XL-3PQ256C |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| 中文描述： | 斯巴達(dá)和Spartan - xL的家庭現(xiàn)場(chǎng)可編程門陣列 |
| 文件頁(yè)數(shù)： | 51/82頁(yè) |
| 文件大?。?/td> | 623K |
| 代理商： | XCS05XL-3PQ256C |
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Spartan and Spartan-XL Families Field Programmable Gate Arrays
DS060 (v1.6) September 19, 2001
Product Specification
www.xilinx.com
1-800-255-7778
51
R
Spartan IOB Output Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuring internal test patterns. Listed below
are representative values. For more specific, more precise,
and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Develop-
ment System) and back-annotated to the simulation netlist.
These path delays, provided as a guideline, have been
extracted from the static timing analyzer report. All timing
parameters assume worst-case operating conditions (sup-
ply voltage and junction temperature). Values are
expressed in nanoseconds unless otherwise noted.
Symbol
Description
Device
Speed Grade
Units
-4
-3
Min
Max
Min
Max
Clocks
T
CH
T
CL
Clock High
All devices
3.0
-
4.0
-
ns
Clock Low
All devices
3.0
-
4.0
-
ns
Propagation Delays - TTL Outputs
(1,2)
T
OKPOF
T
OKPOS
T
OPF
T
OPS
T
TSHZ
T
TSONF
T
TSONS
Setup and Hold Times
Clock (OK) to Pad, fast
All devices
-
3.3
-
4.5
ns
Clock (OK to Pad, slew-rate limited
All devices
-
6.9
-
7.0
ns
Output (O) to Pad, fast
All devices
-
3.6
-
4.8
ns
Output (O) to Pad, slew-rate limited
All devices
-
7.2
-
7.3
ns
3-state to Pad High-Z (slew-rate independent)
All devices
-
3.0
-
3.8
ns
3-state to Pad active and valid, fast
All devices
-
6.0
-
7.3
ns
3-state to Pad active and valid, slew-rate limited
All devices
-
9.6
-
9.8
ns
T
OOK
T
OKO
T
ECOK
T
OKEC
Global Set/Reset
Output (O) to clock (OK) setup time
All devices
2.5
-
3.8
-
ns
Output (O) to clock (OK) hold time
All devices
0.0
-
0.0
-
ns
Clock Enable (EC) to clock (OK) setup time
All devices
2.0
-
2.7
-
ns
Clock Enable (EC) to clock (OK) hold time
All devices
0.0
-
0.5
-
ns
T
MRW
T
RPO
Minimum GSR pulse width
All devices
11.5
13.5
ns
Delay from GSR input to any Pad
XCS05
-
12.0
-
15.0
ns
XCS10
-
12.5
-
15.7
ns
XCS20
-
13.0
-
16.2
ns
XCS30
-
13.5
-
16.9
ns
XCS40
-
14.0
-
17.5
ns
Notes:
1.
2.
3.
Delay adder for CMOS Outputs option (with fast slew rate option): for -3 speed grade, add 1.0 ns; for -4 speed grade, add 0.8 ns.
Delay adder for CMOS Outputs option (with slow slew rate option): for -3 speed grade, add 2.0 ns; for -4 speed grade, add 1.5 ns.
Output timing is measured at ~50% V
threshold, with 50 pF external capacitive loads including test fixture. Slew-rate limited output
rise/fall times are approximately two times longer than fast output rise/fall times.
Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull-up
(default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.
4.
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相關(guān)代理商/技術(shù)參數(shù) |
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| XCS05XL-3PQ256I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS05XL-3PQ280C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
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| XCS05XL-3PQ84C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS05XL-3PQ84I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
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