參數(shù)資料
型號(hào)： XCS05XL-3PQ256C
廠商： Xilinx, Inc.
英文描述： Spartan and Spartan-XL Families Field Programmable Gate Arrays
中文描述： 斯巴達(dá)和Spartan - xL的家庭現(xiàn)場(chǎng)可編程門陣列
文件頁(yè)數(shù)： 47/82頁(yè)
文件大?。?/td> 623K
代理商： XCS05XL-3PQ256C
Spartan and Spartan-XL Families Field Programmable Gate Arrays
DS060 (v1.6) September 19, 2001
Product Specification
www.xilinx.com
1-800-255-7778
47
R
Spartan Pin-to-Pin Output Parameter Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Pin-to-pin timing parameters are
derived from measuring external and internal test patterns
and are guaranteed over worst-case operating conditions
(supply voltage and junction temperature). Listed below are
representative values for typical pin locations and normal
clock loading. For more specific, more precise, and
worst-case guaranteed data, reflecting the actual routing
structure, use the values provided by the static timing ana-
lyzer (TRCE in the Xilinx Development System) and
back-annotated to the simulation netlist. These path delays,
provided as a guideline, have been extracted from the static
timing analyzer report.
Spartan Output Flip-Flop, Clock-to-Out
Symbol
Global Primary Clock to TTL Output using OFF
T
ICKOF
Fast
Description
Device
Speed Grade
-4
Max
Units
-3
Max
XCS05
XCS10
XCS20
XCS30
XCS40
XCS05
XCS10
XCS20
XCS30
XCS40
5.3
5.7
6.1
6.5
6.8
9.0
9.4
9.8
10.2
10.5
8.7
9.1
9.3
9.4
10.2
11.5
12.0
12.2
12.8
12.8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
T
ICKO
Slew-rate limited
Global Secondary Clock to TTL Output using OFF
T
ICKSOF
Fast
XCS05
XCS10
XCS20
XCS30
XCS40
XCS05
XCS10
XCS20
XCS30
XCS40
5.8
6.2
6.6
7.0
7.3
9.5
9.9
10.3
10.7
11.0
9.2
9.6
9.8
9.9
10.7
12.0
12.5
12.7
13.2
14.3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
T
ICKSO
Slew-rate limited
Delay Adder for CMOS Outputs Option
T
CMOSOF
Fast
T
CMOSO
Slew-rate limited
Notes:
1.
Listed above are representative values where one global clock input drives one vertical clock line in each accessible column,and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
2.
Output timing is measured at ~50% V
CC
threshold with 50 pF external capacitive load. For different loads, see
Figure 33
.
3.
OFF = Output Flip-Flop
All devices
All devices
0.8
1.5
1.0
2.0
ns
ns
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XCS05XL-3PQ84I 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays
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