參數(shù)資料
型號: XCS05XL-3PQ256C
廠商: Xilinx, Inc.
英文描述: Spartan and Spartan-XL Families Field Programmable Gate Arrays
中文描述: 斯巴達(dá)和Spartan - xL的家庭現(xiàn)場可編程門陣列
文件頁數(shù): 49/82頁
文件大小: 623K
代理商: XCS05XL-3PQ256C
Spartan and Spartan-XL Families Field Programmable Gate Arrays
DS060 (v1.6) September 19, 2001
Product Specification
www.xilinx.com
1-800-255-7778
49
R
Spartan Pin-to-Pin Input Parameter Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Pin-to-pin timing parameters are
derived from measuring external and internal test patterns
and are guaranteed over worst-case operating conditions
(supply voltage and junction temperature). Listed below are
representative values for typical pin locations and normal
clock loading.
Spartan Primary and Secondary Setup and Hold
Symbol
Input Setup/Hold Times Using Primary Clock and IFF
T
PSUF
/T
PHF
No Delay
Description
Device
Speed Grade
-4
Min
Units
-3
Min
XCS05
XCS10
XCS20
XCS30
XCS40
XCS05
XCS10
XCS20
XCS30
XCS40
1.2 / 1.7
1.0 / 2.3
0.8 / 2.7
0.6 / 3.0
0.4 / 3.5
4.3 / 0.0
4.3 / 0.0
4.3 / 0.0
4.3 / 0.0
5.3 / 0.0
1.8 / 2.5
1.5 / 3.4
1.2 / 4.0
0.9 / 4.5
0.6 / 5.2
6.0 / 0.0
6.0 / 0.0
6.0 / 0.0
6.0 / 0.0
6.8 / 0.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
T
PSU
/T
PH
With Delay
Input Setup/Hold Times Using Secondary Clock and IFF
T
SSUF
/T
SHF
No Delay
XCS05
XCS10
XCS20
XCS30
XCS40
XCS05
XCS10
XCS20
XCS30
XCS40
0.9 / 2.2
0.7 / 2.8
0.5 / 3.2
0.3 / 3.5
0.1 / 4.0
4.0 / 0.0
4.0 / 0.0
4.0 / 0.5
4.0 / 0.5
5.0 / 0.0
1.5 / 3.0
1.2 / 3.9
0.9 / 4.5
0.6 / 5.0
0.3 / 5.7
5.7 / 0.0
5.7 / 0.0
5.7 / 0.5
5.7 / 0.5
6.5 / 0.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
T
SSU
/T
SH
With Delay
Notes:
1.
Setup time is measured with the fastest route and the lightest load. Hold time is measured using the furthest distance and a
reference load of one clock pin per IOB/CLB.
IFF = Input Flip-flop or Latch
2.
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