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| 型號(hào)： | XCCACE-TQG144I |
| 廠商： | Xilinx Inc |
| 文件頁(yè)數(shù)： | 67/69頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC ACE CONTROLLER CHIP TQ144 |
| 產(chǎn)品變化通告： | XCCACE-TQG144I Discontinuation 31/Oct/2011 |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 控制器類型： | ACE 控制器 |
| 電源電壓： | 3 V ~ 3.6 V |
| 電流 - 電源： | 30mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 144-LQFP |
| 供應(yīng)商設(shè)備封裝： | 144-TQFP（20x20） |
| 包裝： | 管件 |
| 其它名稱： | 122-1511-5 |
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System ACE CompactFlash Solution
DS080 (v3.0) April 7, 2014
Product Specification
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
Interfaces Overview
This section discusses the details of each supported Sys-
tem ACE CF controller interface.
CompactFlash Interface (CF)
The CompactFlash interface is the key System ACE CF
controller interface for high-capacity systems. The Com-
pactFlash port can accommodate any standard Compact-
Flash module (up to 8 GB) or Hitachi Microdrives (up to
6 GB), all with the same form factor and board space
requirements.
The use of standard CompactFlash devices gives system
designers access to high-density Flash memory in a very
efficient footprint that does not change with density. Com-
pactFlash is a removable medium which simplifies making
changes to the memory contents or upgrading the memory
density.
The CompactFlash interface is comprised of two sub-com-
ponents: a CompactFlash Controller and a CompactFlash
Arbiter. The CompactFlash Controller detects the presence
and maintains the status of the CompactFlash device. This
Controller also handles all CompactFlash device access
bus cycles, and abstracts and implements CompactFlash
commands such as soft reset, identify drive, and read/write
sector(s). The CompactFlash Arbiter controls the interface
between the MPU and the Configuration JTAG Controller for
access to the CompactFlash data buffer.
When using the CompactFlash card as the configuration
source, the CFGTCK output for the System ACE CF control-
ler device is derived from the CLK input to the System ACE
CF controller. The operating frequency of the CFGTCK is
the same as CLK:
The minimum clock operating frequency is 0 MHz.
The maximum clock operating frequency is either 33
MHz or the maximum JTAG TCK clock speed dictated
by the devices in the JTAG chain and/or the board
design. The lowest of these values should be used.
CompactFlash devices are compliant with multiple read and
write modes. The System ACE CF controller only supports
ATA Common Memory Read and Write functions. Figure 6
and Figure 7, page 8 provide detailed timing information on
these functions.
Figure 6: CompactFlash Common Memory Write Timing Diagram
DS080_09_031301
ADDRESS
REG
DIN
CE
WE
WAIT
T V(WT-WE)
DIN Valid
T V(WT)
T SU(A)
T SU(CE)
T W(WE)
T W(WT)
T SU(D - WEH)
T H(D)
T H(CE)
T REC(WE)
Table 4: Common Memory Write Timing
Item
Symbol
IEEE Symbol
Min (ns)
Max (ns)
Data Setup before WE
TSU(D-WEH)
tDVWH
80
Data Hold following WE
TH(D)
tlWMDX
30
WE Pulse Width
TW(WE)
tWLWH
150
Address Setup Time
TSU(A)
tAVWL
30
CE Setup before WE
TSU(CE)
tELWL
0
Write Recovery Time
TREC(WE)
tWMAX
30
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