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| 型號： | XCCACE-TQG144I |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 31/69頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ACE CONTROLLER CHIP TQ144 |
| 產(chǎn)品變化通告： | XCCACE-TQG144I Discontinuation 31/Oct/2011 |
| 標準包裝： | 60 |
| 控制器類型： | ACE 控制器 |
| 電源電壓： | 3 V ~ 3.6 V |
| 電流 - 電源： | 30mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 144-LQFP |
| 供應商設備封裝： | 144-TQFP（20x20） |
| 包裝： | 管件 |
| 其它名稱： | 122-1511-5 |
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System ACE CompactFlash Solution
DS080 (v3.0) April 7, 2014
37
Product Specification
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
Configuration JTAG Interface (CFGJTAG)
Configuration JTAG Port is the interface between the System ACE CF controller and the target FPGA chain. This port is
accessed when configuring the target FPGA chain of devices via any of the System ACE CF controller interfaces (Test
JTAG, MPU, or CompactFlash). To program or test the FPGA target chain, the data from these interfaces is converted to
IEEE 1149.1 Boundary-Scan (JTAG) serial data.
Typical Configuration Modes
The four System ACE CF controller interfaces are designed to work together in a number of different combinations. This
section discusses typical user configuration modes. A handful of signals determine which interface provides the
configuration data source. Table 26 describes these important signals, and Table 27 shows how they work together to
determine which interface will be used. This is especially important when using multiple interfaces in a design, or when not
using the default values of these signals. The default values of these signals set the CompactFlash interface as the source
of configuration data.
Table 25: System ACE CF Controller TAP Characteristics
Symbol
Parameter
Min
Max
Units
T(TAPTCK)
TSTTMS and TSTTDI setup time before rising edge of TSTTCK
4
ns
T(TCKTAP)
TSTTMS and TSTTDI hold times after TSTTCK
4
ns
T(TCKTDO)
TSTTCK falling edges to TSTTDO output valid
16
ns
F(TSTTCK)
Maximum TSTTCK clock frequency
16.7
MHz
Table 26: Configuration Signals Used for Selecting Configuration Modes and Active Design
Configuration Signal
Description
Default
CFGMODE
Pin or MPU register bit
CFGMODEPIN = 1
CFGMODE Register Bit = 0
CFGADDR[2:0]
Pins or MPU register bits
0
CFGSEL
MPU register bit
0
CFGSTART
MPU register bit
0
CFGRESET
MPU register bit (CFGRESET is a subset of the RESET pin)
0
FORCECFGADDR
MPU register bit (Overrides value on CFGADDR [2:0] pins)
0
FORCECFGMODE
MPU register bit (Overrides value on CFGMODEPIN)
0
Table 27: Active Configuration Modes
Configuration Interface
CFGMODE(1)
CFGSEL
CFGSTART
CFGRESET
CompactFlash (Configure from CF immediately after CFGRESET)
10
X(2)
0
CompactFlash (Configure from CF after receiving MPU start signal)
00
1
0
Microprocessor (Configure from MPU after receiving MPU start signal)
11
1
0
Microprocessor (Configure from MPU)
11
X
0
Test JTAG (Configure using the TSTJTAG port)(3)
XX
X
Notes:
1.
The FORCECFGMODE bit in the CONTROLREG register of the MPU interface can be used to force the CFGMODE register bit to
override the System ACE CF controller CFGMODEPIN.
2.
An X entry indicates “don’t care”.
3.
The Test JTAG configuration mode is active regardless of the pin settings as long as none of the other configuration modes are in
operation.
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