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| 型號(hào)： | XCCACE-TQG144I |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 40/69頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ACE CONTROLLER CHIP TQ144 |
| 產(chǎn)品變化通告： | XCCACE-TQG144I Discontinuation 31/Oct/2011 |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 控制器類型： | ACE 控制器 |
| 電源電壓： | 3 V ~ 3.6 V |
| 電流 - 電源： | 30mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 144-LQFP |
| 供應(yīng)商設(shè)備封裝： | 144-TQFP（20x20） |
| 包裝： | 管件 |
| 其它名稱： | 122-1511-5 |
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System ACE CompactFlash Solution
DS080 (v3.0) April 7, 2014
45
Product Specification
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
Read Data Buffer Control Flow Process
The control flow process for reading from the data buffer is
shown in Figure 25. The System ACE data buffer is imple-
mented as a 32-byte (16-word) deep FIFO that is aliased
across a range of MPU byte addresses (40h through 7Fh) in
order to facilitate burst transfers across the MPU interface.
Sector data is read from the data buffer by first waiting for
the buffer to become ready (i.e., full of sector data), as
shown in Figure 26, page 46. Once the buffer is ready, then
all 32 bytes can be read from the buffer from alternating
even and odd byte addresses. Reading from an odd byte
address while in BYTE mode causes the FIFO to increment
the data word to the next available word in the FIFO. Read-
ing from any data buffer address while in WORD mode will
cause the FIFO to increment.
Figure 25: Read Data Buffer Control Flow Process
Read data word
from buffer
Decrement Data
Count variable
Data Count
equal to 0?
Buffer is written.
Return success.
Yes
No
Wait for Buffer Ready
Read Data Buffer
Initialize Data
Count variable*
*Set Data Count variable equal to
the number of data items in a buffer
(e.g., 16 bytes or 32 words)
Read data bits 7:0 from byte address 40h
Read data bits 15:8 from byte address 41h
(Note that the following conditions must
be valid for a data read to occur from the
CompactFlash data buffer:
1. The data buffer must be ready
2. A single read from byte address 41h
must occur that will cause the entire 16-
bit data register to be overwritten by the
buffer with new data)
DS080_51_051701
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