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參數(shù)資料
| 型號： | XC9500 |
| 廠商： | Xilinx, Inc. |
| 英文描述： | XC9500 In-System Programmable CPLD Family |
| 中文描述： | XC9500在系統(tǒng)可編程CPLD系列 |
| 文件頁數(shù)： | 9/16頁 |
| 文件大?。?/td> | 172K |
| 代理商： | XC9500 |
XC9500 In-System Programmable CPLD Family
DS063 (v5.1) September 22, 2003
Product Specification
www.xilinx.com
1-800-255-7778
9
R
Fast CONNECT Switch Matrix
The Fast CONNECT switch matrix connects signals to the
FB inputs, as shown in
Figure 9
. All IOB outputs (corre-
sponding to user pin inputs) and all FB outputs drive the
Fast CONNECT matrix. Any of these (up to a FB fan-in limit
of 36) may be selected, through user programming, to drive
each FB with a uniform delay.
The Fast CONNECT switch matrix is capable of combining
multiple internal connections into a single wired-AND output
before driving the destination FB. This provides additional
logic capability and increases the effective logic fan-in of the
destination FB without any additional timing delay. This
capability is available for internal connections originating
from FB outputs only. It is automatically invoked by the
development software where applicable.
Figure 9:
Fast CONNECT Switch Matrix
DS063_09_110501
Function Block
Fast CONNECT
Switch Matrix
(36)
I/O
Function Block
Wired-AND
Capability
I/O Block
18
18
I/O Block
(36)
I/O
D/T Q
D/T Q
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