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參數(shù)資料
| 型號(hào)： | XC9500 |
| 廠商： | Xilinx, Inc. |
| 英文描述： | XC9500 In-System Programmable CPLD Family |
| 中文描述： | XC9500在系統(tǒng)可編程CPLD系列 |
| 文件頁數(shù)： | 4/16頁 |
| 文件大小： | 172K |
| 代理商： | XC9500 |
XC9500 In-System Programmable CPLD Family
4
www.xilinx.com
1-800-255-7778
DS063 (v5.1) September 22, 2003
Product Specification
R
Macrocell
Each XC9500 macrocell may be individually configured for
a combinatorial or registered function. The macrocell and
associated FB logic is shown in
Figure 3
.
Five direct product terms from the AND-array are available
for use as primary data inputs (to the OR and XOR gates) to
implement combinatorial functions, or as control inputs
including clock, set/reset, and output enable. The product
term allocator associated with each macrocell selects how
the five direct terms are used.
The macrocell register can be configured as a D-type or
T-type flip-flop, or it may be bypassed for combinatorial
operation. Each register supports both asynchronous set
and reset operations. During power-up, all user registers
are initialized to the user-defined preload state (default to 0
if unspecified).
Figure 3:
XC9500 Macrocell Within Function Block
DS063_03_110501
To
Fast CONNECTII
Switch Matrix
Additional
Product
Terms
(from other
macrocells)
Global
Set/Reset
Global
Clocks
Additional
Product
Terms
(from other
macrocells)
To
I/O Blocks
OUT
1
0
36
3
PTOE
D/T
Q
S
R
Product
Term
Allocator
Product Term Set
Product Term Clock
Product Term Reset
Product Term OE
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