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參數資料
| 型號： | XC9500 |
| 廠商： | Xilinx, Inc. |
| 英文描述： | XC9500 In-System Programmable CPLD Family |
| 中文描述： | XC9500在系統(tǒng)可編程CPLD系列 |
| 文件頁數： | 15/16頁 |
| 文件大?。?/td> | 172K |
| 代理商： | XC9500 |
XC9500 In-System Programmable CPLD Family
DS063 (v5.1) September 22, 2003
Product Specification
www.xilinx.com
1-800-255-7778
15
R
Power-Up Characteristics
The XC9500 devices are well behaved under all operating
conditions. During power-up each XC9500 device employs
internal circuitry which keeps the device in the quiescent
state until the V
CCINT
supply voltage is at a safe level
(approximately 3.8V). During this time, all device pins and
JTAG pins are disabled and all device outputs are disabled
with the IOB pull-up resistors (~10K ohms) enabled, as
shown in
Table 5
. When the supply voltage reaches a safe
level, all user registers become initialized (typically within
100
μ
s for 9536, 95144, 200
μ
s for 95216, and 300
μ
s for
95288), and the device is immediately available for opera-
tion, as shown in
Figure 16
.
If the device is in the erased state (before any user pattern
is programmed), the device outputs remain disabled with
the IOB pull-up resistors enabled. The JTAG pins are
enabled to allow the device to be programmed at any time.
If the device is programmed, the device inputs and outputs
take on their configured states for normal operation. The
JTAG pins are enabled to allow device erasure or bound-
ary-scan tests at any time.
Development System Support
The XC9500 CPLD family is fully supported by the develop-
ment systems available from Xilinx and the Xilinx Alliance
Program vendors.
The designer can create the design using ABEL, schemat-
ics, equations, VHDL, or Verilog in a variety of software
front-end tools. The development system can be used to
implement the design and generate a JEDEC bitmap which
can be used to program the XC9500 device. Each develop-
ment system includes JTAG download software that can be
used to program the devices via the standard JTAG inter-
face and a download cable.
FastFLASH Technology
An advanced CMOS Flash process is used to fabricate all
XC9500 devices. Specifically developed for Xilinx in-system
programmable CPLDs, the FastFLASH process provides
high performance logic capability, fast programming times,
and endurance of 10,000 program/erase cycles.
Figure 16:
Device Behavior During Power-up
V
CCINT
No
Power
3.8 V
(Typ)
0V
No
Power
Quiescent
State
Quiescent
State
User Operation
Initialization of User Registers
DS063_16_110501
Table 4:
Timing Model Parameters
Parameter
T
PD
T
SU
T
CO
T
PSU
T
PCO
T
SYSTEM
Notes:
1.
S = the logic span of the function, as defined in the text.
Description
Product Term
Allocator
(1)
+ T
PTA
*
S
+ T
PTA
*
S
-
+ T
PTA
*
S
-
+ T
PTA
*
S
Macrocell
Low-Power Setting
+ T
LP
+ T
LP
-
+ T
LP
-
+ T
LP
Output
Slew-Limited
Setting
+ T
SLEW
–
+ T
SLEW
-
+ T
SLEW
-
Propagation Delay
Global Clock Setup Time
Global Clock-to-output
Product Term Clock Setup Time
Product Term Clock-to-output
Internal System Cycle Period
Table 5:
XC9500 Device Characteristics
Device Circuitry
IOB Pull-up Resistors
Device Outputs
Quiescent State
Enabled
Disabled
Erased Device Operation
Enabled
Disabled
Valid User Operation
Disabled
As Configured
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