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參數(shù)資料
| 型號： | XC9500 |
| 廠商： | Xilinx, Inc. |
| 英文描述： | XC9500 In-System Programmable CPLD Family |
| 中文描述： | XC9500在系統(tǒng)可編程CPLD系列 |
| 文件頁數(shù)： | 11/16頁 |
| 文件大小： | 172K |
| 代理商： | XC9500 |
XC9500 In-System Programmable CPLD Family
DS063 (v5.1) September 22, 2003
Product Specification
www.xilinx.com
1-800-255-7778
11
R
Each output has independent slew rate control. Output
edge rates may be slowed down to reduce system noise
(with an additional time delay of T
SLEW
) through program-
ming. See
Figure 11
.
Each IOB provides user programmable ground pin capabil-
ity. This allows device I/O pins to be configured as additional
ground pins. By tying strategically located programmable
ground pins to the external ground connection, system
noise generated from large numbers of simultaneous
switching outputs may be reduced.
A control pull-up resistor (typically 10K ohms) is attached to
each device I/O pin to prevent them from floating when the
device is not in normal user operation. This resistor is active
during device programming mode and system power-up. It
is also activated for an erased device. The resistor is deac-
tivated during normal operation.
The output driver is capable of supplying 24 mA output
drive. All output drivers in the device may be configured for
either 5V TTL levels or 3.3V levels by connecting the device
output voltage supply (V
CCIO
) to a 5V or 3.3V voltage sup-
ply.
Figure 12
shows how the XC9500 device can be used in
5V only and mixed 3.3V/5V systems.
Pin-Locking Capability
The capability to lock the user defined pin assignments dur-
ing design changes depends on the ability of the architec-
ture to adapt to unexpected changes. The XC9500 devices
have architectural features that enhance the ability to
accept design changes while maintaining the same pinout.
The XC9500 architecture provides maximum routing within
the Fast CONNECT switch matrix, and incorporates a flexi-
ble Function Block that allows block-wide allocation of avail-
able product terms. This provides a high level of confidence
of maintaining both input and output pin assignments for
unexpected design changes.
For extensive design changes requiring higher logic capac-
ity than is available in the initially chosen device, the new
design may be able to fit into a larger pin-compatible device
using the same pin assignments. The same board may be
used with a higher density device without the expense of
board rework
Figure 11:
Output slew-Rate for (a) Rising and (b) Falling Outputs
Figure 12:
XC9500 Devices in (a) 5V Systems and (b) Mixed 5V/3.3V Systems
Time
0
0
1.5V
Standard
Output
Voltage
(a)
Slew-Rate Limited
Time
Output
Voltage
(b)
Standard
Slew-Rate Limited
T
SLEW
T
SLEW
1.5V
DS063_11_110501
IN
OUT
5V
GND
(b)
3.3V
XC9500
CPLD
V
CCINT
V
CCIO
5V
0V
3.3V
0V
3.6V
0V
3.3V
0V
3.3V
DS063_12_110501
3.3V
5V TTL or
5V CMOS or
IN
OUT
5V
GND
(a)
5V TTL
XC9500
CPLD
V
CCINT
V
CCIO
5V
0V
–4V
0V
3.6V
0V
3.3V
0V
3.3V
5V TTL or
5V CMOS or
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