Spartan-3AN FPGA Family: Pinout Descriptions
DS557 (v4.1) April 1, 2011
Product Specification
75
TQG144: 144-lead Thin Quad Flat Package
The XC3S50AN is available in the 144-lead thin quad flat package, TQG144.
Table 68 lists all the package pins. They are sorted by bank number and then by pin name. Pins that form a differential I/O
pair appear together in the table. The table also shows the pin number for each pin and the pin type (as defined in
Table 62).
The XC3S50AN does not support the address output pins for the Byte-wide Peripheral Interface (BPI) configuration mode.
An electronic version of this package pinout table and footprint diagram is available for download from the Xilinx website at:
Pinout Table
Table 68: Spartan-3AN TQG144 Pinout
Bank
Pin Name
Pin
Type
0
IO_0
P142
I/O
0
IO_L01N_0
P111
I/O
0
IO_L01P_0
P110
I/O
0
IO_L02N_0
P113
I/O
0
IO_L02P_0/VREF_0
P112
VREF
0
IO_L03N_0
P117
I/O
0
IO_L03P_0
P115
I/O
0
IO_L04N_0
P116
I/O
0
IO_L04P_0
P114
I/O
0
IO_L05N_0
P121
I/O
0
IO_L05P_0
P120
I/O
0
IO_L06N_0/GCLK5
P126
GCLK
0
IO_L06P_0/GCLK4
P124
GCLK
0
IO_L07N_0/GCLK7
P127
GCLK
0
IO_L07P_0/GCLK6
P125
GCLK
0
IO_L08N_0/GCLK9
P131
GCLK
0
IO_L08P_0/GCLK8
P129
GCLK
0
IO_L09N_0/GCLK11
P132
GCLK
0
IO_L09P_0/GCLK10
P130
GCLK
0
IO_L10N_0
P135
I/O
0
IO_L10P_0
P134
I/O
0
IO_L11N_0
P139
I/O
0
IO_L11P_0
P138
I/O
0
IO_L12N_0/PUDC_B
P143
DUAL
0
IO_L12P_0/VREF_0
P141
VREF
0
IP_0
P140
INPUT
0
IP_0/VREF_0
P123
VREF
0
VCCO_0
P119
VCCO
0
VCCO_0
P136
VCCO
1
IO_1
P79
I/O
1
IO_L01N_1/LDC2
P78
DUAL
1
IO_L01P_1/HDC
P76
DUAL
1
IO_L02N_1/LDC0
P77
DUAL
1
IO_L02P_1/LDC1
P75
DUAL
1
IO_L03N_1
P84
I/O
1
IO_L03P_1
P82
I/O
1
IO_L04N_1/RHCLK1
P85
RHCLK
1
IO_L04P_1/RHCLK0
P83
RHCLK
1
IO_L05N_1/TRDY1/RHCLK3
P88
RHCLK
1
IO_L05P_1/RHCLK2
P87
RHCLK
1
IO_L06N_1/RHCLK5
P92
RHCLK
1
IO_L06P_1/RHCLK4
P90
RHCLK
1
IO_L07N_1/RHCLK7
P93
RHCLK
1
IO_L07P_1/IRDY1/RHCLK6
P91
RHCLK
1
IO_L08N_1
P98
I/O
1
IO_L08P_1
P96
I/O
1
IO_L09N_1
P101
I/O
1
IO_L09P_1
P99
I/O
1
IO_L10N_1
P104
I/O
1
IO_L10P_1
P102
I/O
1
IO_L11N_1
P105
I/O
1
IO_L11P_1
P103
I/O
1
IP_1/VREF_1
P80
VREF
1
IP_1/VREF_1
P97
VREF
1
VCCO_1
P86
VCCO
1
VCCO_1
P95
VCCO
2
IO_2/MOSI/CSI_B
P62
DUAL
2
IO_L01N_2/M0
P38
DUAL
2
IO_L01P_2/M1
P37
DUAL
2
IO_L02N_2/CSO_B
P41
DUAL
2
IO_L02P_2/M2
P39
DUAL
2
IO_L03N_2/VS1
P44
DUAL
2
IO_L03P_2/RDWR_B
P42
DUAL
2
IO_L04N_2/VS0
P45
DUAL
2
IO_L04P_2/VS2
P43
DUAL
2
IO_L05N_2/D7
P48
DUAL
Table 68: Spartan-3AN TQG144 Pinout (Cont’d)
Bank
Pin Name
Pin
Type