參數(shù)資料
型號(hào)： XC3S400AN-5FTG256C
廠商： Xilinx Inc
文件頁數(shù)： 29/123頁
文件大小： 0K
描述： IC FPGA SPARTAN-3AN 256FTBGA
標(biāo)準(zhǔn)包裝： 90
系列： Spartan®-3AN
LAB/CLB數(shù)： 896
邏輯元件/單元數(shù)： 8064
RAM 位總計(jì)： 368640
輸入/輸出數(shù)： 195
門數(shù)： 400000
電源電壓： 1.14 V ~ 1.26 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 256-LBGA
供應(yīng)商設(shè)備封裝： 256-FTBGA
Spartan-3AN FPGA Family: DC and Switching Characteristics
DS557 (v4.1) April 1, 2011
Product Specification
13
Power Supply Specifications
Table 7: Supply Voltage Thresholds for Power-On Reset
Symbol
Description
Min
Max
Units
VCCINTT
Threshold for the VCCINT supply
0.4
1.0
V
VCCAUXT
Threshold for the VCCAUX supply
1.0
2.0
V
VCCO2T
Threshold for the VCCO Bank 2 supply
1.0
2.0
V
Notes:
1.
When configuring from the In-System Flash, VCCAUX must be in the recommended operating range; on power-up make sure VCCAUX
reaches at least 3.0V before INIT_B goes High to indicate the start of configuration. VCCINT, VCCAUX, and VCCO supplies to the FPGA can
be applied in any order if this requirement is met. However, an external configuration source might have specific requirements. Check the
data sheet for the attached configuration source. Apply VCCINT last for lowest overall power consumption (see the chapter called “Powering
Spartan-3 Generation FPGAs” in UG331 for more information).
2.
To ensure successful power-on, VCCINT, VCCO Bank 2, and VCCAUX supplies must rise through their respective threshold-voltage ranges with
no dips at any point.
Table 8: Supply Voltage Ramp Rate
Symbol
Description
Min
Max
Units
VCCINTR
Ramp rate from GND to valid VCCINT supply level
0.2
100
ms
VCCAUXR
Ramp rate from GND to valid VCCAUX supply level
0.2
100
ms
VCCO2R
Ramp rate from GND to valid VCCO Bank 2 supply level
0.2
100
ms
Notes:
1.
When configuring from the In-System Flash, VCCAUX must be in the recommended operating range; on power-up make sure VCCAUX
reaches at least 3.0V before INIT_B goes High to indicate the start of configuration. VCCINT, VCCAUX, and VCCO supplies to the FPGA can
be applied in any order if this requirement is met. However, an external configuration source might have specific requirements. Check the
data sheet for the attached configuration source. Apply VCCINT last for lowest overall power consumption (see the chapter called “Powering
Spartan-3 Generation FPGAs” in UG331 for more information).
2.
To ensure successful power-on, VCCINT, VCCO Bank 2, and VCCAUX supplies must rise through their respective threshold-voltage ranges with
no dips at any point.
Table 9: Supply Voltage Levels Necessary for Preserving CMOS Configuration Latch (CCL) Contents and RAM Data
Symbol
Description
Min
Units
VDRINT
VCCINT level required to retain CMOS Configuration Latch (CCL) and RAM data
1.0
V
VDRAUX
VCCAUX level required to retain CMOS Configuration Latch (CCL) and RAM data
2.0
V
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