參數(shù)資料
型號(hào)： X1202
英文描述： Real Time Clock/Calendar/Alarms/CPU Supervisor(實(shí)時(shí)時(shí)鐘/日歷/鬧鐘/CPU監(jiān)控電路)
中文描述： 實(shí)時(shí)時(shí)鐘/日歷/報(bào)警/ CPU監(jiān)控（實(shí)時(shí)時(shí)鐘/日歷/鬧鐘/ CPU的監(jiān)控電路）
文件頁(yè)數(shù)： 13/23頁(yè)
文件大小： 340K
代理商： X1202
X1202
Characteristics subject to change without notice.
13 of 23
REV 1.1.8 5/17/01
www.xicor.com
Random Read
Random read operation allows the master to access
any memory location in the array. Prior to issuing the
slave address byte with the R/W bit set to one, the
master must first perform a “dummy” write operation.
The master issues the start condition and the slave
address byte, receives an acknowledge, then issues
the CCR address bytes. After acknowledging receipt of
the CCR address bytes, the master immediately issues
another start condition and the slave address byte with
the R/W bit set to one. This is followed by an acknowl-
edge from the device and then by the eight bit word.
The master terminates the read operation by not
responding with an acknowledge and then issuing a
stop condition. Refer to Figure 15 for the address,
acknowledge, and data transfer sequence.
In a similar operation called “Set Current Address,” the
device sets the address if a stop is issued instead of
the second start shown in Figure 16. The X1202 then
goes into standby mode after the stop and all bus
activity will be ignored until a start is detected. This
operation loads the new address into the address
counter. The next current address read operation will
read from the newly loaded address. This operation
could be useful if the master knows the next address it
needs to read, but is not ready for the data.
Figure 15. Random Address Read Sequence
Figure 16. Sequential Read Sequence
1
Slave
Address
CCR
Address 1
A
C
K
A
C
K
S
t
a
r
t
S
t
o
p
Slave
Address
Data
A
C
K
S
t
a
r
t
SDA Bus
Signals from
the Slave
Signals from
the Master
A
C
K
CCR
Address 0
1
1
1
1
0
1
1
0 0 0 0 0 0 0 0
1 1 0 1 1 1 1 1
Data (2)
S
t
o
p
Slave
Address
Data (n)
A
C
K
A
C
K
SDA Bus
Signals from
the Slave
Signals from
the Master
1
Data (n-1)
(n is any integer greater than 1)
Data (1)
A
C
K
A
C
K
Sequential Read
Sequential reads can be initiated as either a current
address read or random address read. The first data
byte is transmitted as with the other modes; however,
the master now responds with an acknowledge, indicat-
ing it requires additional data. The device continues to
output data for each acknowledge received. The master
terminates the read operation by not responding with
an acknowledge and then issuing a stop condition.
The data output is sequential, with the data from
address n followed by the data from address n + 1. The
address counter for read operations increments auto-
matically, allowing the entire register contents to be
serially read during one operation. At the end of the
register space the counter “rolls over” to the first location
in the register and the device continues to output data
for each acknowledge received. Refer to Figure 18 for
the acknowledge and data transfer sequence.
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