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參數(shù)資料
| 型號： | X1202 |
| 英文描述： | Real Time Clock/Calendar/Alarms/CPU Supervisor(實時時鐘/日歷/鬧鐘/CPU監(jiān)控電路) |
| 中文描述： | 實時時鐘/日歷/報警/ CPU監(jiān)控（實時時鐘/日歷/鬧鐘/ CPU的監(jiān)控電路） |
| 文件頁數(shù)： | 12/23頁 |
| 文件大?。?/td> | 340K |
| 代理商： | X1202 |
X1202
Characteristics subject to change without notice.
12 of 23
REV 1.1.8 5/17/01
www.xicor.com
Figure 13. Acknowledge Polling Sequence
READ OPERATIONS
There are three basic read operations: Current
Address Read, Random Read, and Sequential Read.
Current Address Read
Internally the device contains an address counter that
maintains the address of the last word read incrimi-
nated by one. Therefore, if the last read was to address
n, the next read operation would access data from
address n + 1.
Upon receipt of the slave address byte with the R/W bit
set to one, the device issues an acknowledge and then
transmits the eight bits of the data byte. The master
terminates the read operation when it does not
respond with an acknowledge during the ninth clock
and then issues a stop condition. Refer to Figure 14 for
the address, acknowledge, and data transfer sequence.
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read
operation, the master must either issue a stop condi-
tion during the ninth cycle or hold SDA HIGH during
the ninth clock cycle and then issue a stop condition.
ACK
Returned
Issue Slave
Address Byte
(Read or Write)
Byte Load Completed
by Issuing STOP.
Enter ACK Polling
Issue STOP
Issue START
NO
YES
Issue STOP
NO
Continue Normal
Read or Write
Command
Sequence
PROCEED
YES
Nonvolatile Write
Cycle Complete.
Continue Command
Sequence
Figure 14. Current Address Read Sequence
S
t
a
r
t
S
t
o
p
Slave
Address
Data
A
C
K
SDA Bus
Signals from
the Slave
Signals from
the Master
1
1
1
1
1
0
1
1
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