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參數(shù)資料
| 型號(hào)： | X1202 |
| 英文描述： | Real Time Clock/Calendar/Alarms/CPU Supervisor(實(shí)時(shí)時(shí)鐘/日歷/鬧鐘/CPU監(jiān)控電路) |
| 中文描述： | 實(shí)時(shí)時(shí)鐘/日歷/報(bào)警/ CPU監(jiān)控（實(shí)時(shí)時(shí)鐘/日歷/鬧鐘/ CPU的監(jiān)控電路） |
| 文件頁數(shù)： | 11/23頁 |
| 文件大?。?/td> | 340K |
| 代理商： | X1202 |
X1202
Characteristics subject to change without notice.
11 of 23
REV 1.1.8 5/17/01
www.xicor.com
Figure 11. Byte Write Sequence
Figure 12. Page Write Sequence
S
t
a
r
t
S
t
o
p
Slave
Address
CCR
Address 1
Data
A
C
K
A
C
K
SDA Bus
Signals from
the Slave
Signals from
the Master
0
CCR
Address 0
1
1
1
1
0
1
1
0 0 0 0 0 0 0 0
A
C
K
A
C
K
CCR
Address 0
S
t
a
r
t
S
t
o
p
Slave
Address
CCR
Address 1
Data
(n)
A
C
K
A
C
K
A
C
K
SDA Bus
Signals from
the Slave
Signals from
the Master
0
Data
(1)
A
C
K
(1
≤
n 64)
1
1
1
1
0
1
1
0 0 0 0 0 0 0 0
After the receipt of each byte, the X1202 responds with
an acknowledge, and the address is internally incrimi-
nated by one. When the counter reaches the end of the
page, it “rolls over” and goes back to the first address
on the same page. If the master supplies more than 8
bytes of data, then the previously loaded data is over
written by the new data, one byte at a time. The master
terminates the data byte loading by issuing a stop con-
dition, which causes the device to begin the non vola-
tile write cycle. As with the byte write operation, all
inputs are disabled until completion of the internal write
cycle. Refer to Figure 12 for the address, acknowledge,
and data transfer sequence.
Stops and Write Modes
Stop conditions that terminate write operations must
be sent by the master after sending at least 1 full data
byte and its associated ACK signal. If a stop is issued
in the middle of a data byte, or before 1 full data byte +
ACK is sent, then the device will reset itself without
performing the write. The contents of the array will not
be affected.
Acknowledge Polling
The disabling of the inputs during non volatile write
cycles can be used to take advantage of the typical
5ms write cycle time. Once the stop condition is issued
to indicate the end of the master’s byte load operation,
the device initiates the internal non volatile write cycle.
Acknowledge polling can be initiated immediately. To
do this, the master issues a start condition followed by
the slave address byte for a write or read operation. If
the device is still busy with the non volatile write cycle
then no ACK will be returned. If the device has com-
pleted the write operation, an ACK will be returned and
the host can then proceed with the read or write opera-
tion. Refer to the flow chart in Figure 13.
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