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REV 1.1.8 5/17/01
Characteristics subject to change without notice.
1 of 23
www.xicor.com
X1202
2-Wire
RTC
Real Time Clock/Calendar/Alarms/CPU Supervisor
FEATURES
Selectable watchdog timer (0.25s, 0.75s, 1.75s, off)
Power on reset (250ms)
Programmable low voltage reset
2 polled alarms
—Settable on the second, minute, hour, day,
month, or day of the week
2-wire interface interoperable with I
—400kHz data transfer rate
Secondary power supply input with internal
switch-over circuitry
Low power CMOS
—<1μA operating current
—<3mA active current during program
—<400μA active current during data read
Single byte write capability
Typical nonvolatile write cycle time: 5ms
High reliability
Small package options
—8-lead SOIC package, 8-lead TSSOP package
2
C
DESCRIPTION
The X1202 is a Real Time Clock with Clock/Calendar/
CPU Supervisor circuits and two polled alarms. The dual
port clock and alarm registers allow the clock to oper-
ate, without loss of accuracy, even during read and
write operations.
The clock/calendar provides functionality that is con-
trollable and readable through a set of registers. The
clock, using a low-cost 32.768kHz crystal input, accu-
rately tracks the time in seconds, minutes, hours, date,
day, month and years. It has leap year correction and
automatic adjustment for months with less than 31
days.
The X1202 provides a watchdog timer with 3 selectable
time out periods and off. The watchdog activates a
RESET pin when it expires. The reset also goes active
when V
CC
drops below a fixed trip point. There are two
alarms where a match is monitored by polling status bits.
The device offers a backup power input pin. This V
pin allows the device to be backed up by a non-
rechargeable battery. The RTC is fully operational from
1.8 to 5.5 volts.
BACK
BLOCK DIAGRAM
X1
X2
Oscillator
Frequency
Divider
Timer
Calendar
Logic
8
32.768kHz
Control
Registers
(EEPROM)
1Hz
Time
Keeping
Registers
(SRAM)
Alarm Regs
(EEPROM)
Compare
M
RESET
Control
Decode
Logic
Alarm
SCL
SDA
Serial
Interface
Decoder
Interrupt Enable
Registers
(SRAM)
Status
Alarm