參數(shù)資料
型號: W9864G6IH-6
廠商: WINBOND ELECTRONICS CORP
元件分類: DRAM
英文描述: 4M X 16 DDR DRAM, 5 ns, PDSO54
封裝: 0.400 INCH, ROHS COMPLIANT, TSOP2-54
文件頁數(shù): 9/44頁
文件大?。?/td> 666K
代理商: W9864G6IH-6
W9864G6IH
Publication Release Date: Mar. 22, 2010
- 17 -
Revision A11
8. These parameters account for the number of clock cycles and depend on the operating frequency
of the clock, as follows the number of clock cycles = specified value of timing/ clock period (count
fractions as whole number)
(1)
tCH is the pulse width of CLK measured from the positive edge to the negative edge referenced to VIH (min.).
tCL is the pulse width of CLK measured from the negative edge to the positive edge referenced to VIL (max.).
(2)A.C Latency Characteristics
CKE to clock disable (CKE Latency)
1
tCK
DQM to output to HI-Z (Read DQM Latency)
2
DQM to output to HI-Z (Write DQM Latency)
0
Write command to input data (Write Data Latency)
0
CS
to Command input ( CS Latency)
0
Precharge to DQ Hi-Z Lead time
CL = 2
2
CL = 3
3
Precharge to Last Valid data out
CL = 2
1
CL = 3
2
Bust Stop Command to DQ Hi-Z Lead time
CL = 2
2
CL = 3
3
Bust Stop Command to Last Valid Data out
CL = 2
1
CL = 3
2
Read with Auto-precharge Command to Active/Ref Command
CL = 2
BL + tRP
tCK + nS
CL = 3
BL + tRP
Write with Auto-precharge Command to Active/Ref Command
CL = 2
(BL+1) + tRP
CL = 3
(BL+1) + tRP
9. Assumed input rise and fall time (tT ) = 1nS.
If tr & tf is longer than 1nS, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]nS should be added to the parameter
( The
tT maximum can’t be more than 10nS for low frequency application. )
10. If clock rising time (tT) is longer than 1nS, (tT/2-0.5)nS should be added to the parameter.
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