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參數資料
| 型號： | W9864G6IH-6 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | DRAM |
| 英文描述： | 4M X 16 DDR DRAM, 5 ns, PDSO54 |
| 封裝： | 0.400 INCH, ROHS COMPLIANT, TSOP2-54 |
| 文件頁數： | 3/44頁 |
| 文件大?。?/td> | 666K |
| 代理商： | W9864G6IH-6 |
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W9864G6IH
Publication Release Date: Mar. 22, 2010
- 11 -
Revision A11
7.17 Power Down Mode
The Power Down mode is initiated by holding CKE low. All of the receiver circuits except CKE are
gated off to reduce the power. The Power Down mode does not perform any refresh operations,
therefore the device can not remain in Power Down mode longer than the Refresh period (tREF) of the
device.
The Power Down mode is exited by bringing CKE high. When CKE goes high, a No Operation
Command is required on the next rising clock edge, depending on tCK. The input buffers need to be
enabled with CKE held high for a period equal to tCKS (min.) + tCK (min.).
7.18 No Operation Command
The No Operation Command should be used in cases when the SDRAM is in a idle or a wait state to
prevent the SDRAM from registering any unwanted commands between operations. A No Operation
Command is registered when CS is low with RAS , CAS , and WE held high at the rising edge of
the clock. A No Operation Command will not terminate a previous operation that is still executing,
such as a burst read or write cycle.
7.19 Deselect Command
The Deselect Command performs the same function as a No Operation Command. Deselect
Command occurs when CS is brought high, the RAS , CAS , and WE signals become don't Care.
7.20 Clock Suspend Mode
During normal access mode, CKE must be held high enabling the clock. When CKE is registered low
while at least one of the banks is active, Clock Suspend Mode is entered. The Clock Suspend mode
deactivates the internal clock and suspends any clocked operation that was currently being executed.
There is a one clock delay between the registration of CKE low and the time at which the SDRAM
operation suspends. While in Clock Suspend mode, the SDRAM ignores any new commands that are
issued. The Clock Suspend mode is exited by bringing CKE high. There is a one clock cycle delay
from when CKE returns high to when Clock Suspend mode is exited.
相關PDF資料 |
PDF描述 |
|---|---|
| WA-1RX33-A4 | SNAP ACTING/LIMIT SWITCH |
| WA-A325CBM | Peripheral Interface |
| WA-A325CPC | Peripheral Interface |
| WA-A325CPI | Peripheral Interface |
| WA-A325CPM | Peripheral Interface |
相關代理商/技術參數 |
參數描述 |
|---|---|
| W9864G6IH-6I | 制造商:Winbond Electronics Corp 功能描述:DRAM Chip SDRAM 64M-Bit 4Mx16 3.3V |
| W9864G6IH-7 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:1M 】 4BANKS 】 16BITS SDRAM |
| W9864G6IH-7S | 制造商:WINBOND 制造商全稱:Winbond 功能描述:1M 】 4BANKS 】 16BITS SDRAM |
| W9864G6JB-6 | 制造商:Winbond Electronics Corp 功能描述:IC SDRAM 64MBIT 166MHZ 制造商:Winbond Electronics Corp 功能描述:IC SDRAM 64MBIT 166MHZ 60VFBGA |
| W9864G6JH | 制造商:WINBOND 制造商全稱:Winbond 功能描述:1M ? 4 BANKS ? 16 BITS SDRAM |
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