參數(shù)資料
型號： W981216DH-75
廠商： WINBOND ELECTRONICS CORP
元件分類： DRAM
英文描述： 8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PDSO54
封裝： 0.400 INCH, 0.80 MM PITCH, TSOP2-54
文件頁數(shù)： 12/44頁
文件大?。?/td> 1221K
代理商： W981216DH-75
W981216DH / W9812G6DH
- 2 -
13.
TIMING WAVEFORMS ............................................................................................................. 18
13.1
Command Input Timing ................................................................................................ 18
13.2
Read Timing.................................................................................................................. 19
13.3
Control Timing of Input/Output Data............................................................................. 20
13.4
Mode Register Set Cycle .............................................................................................. 21
14.
OPERATING TIMING EXAMPLE ............................................................................................. 22
14.1
Interleaved Bank Read (Burst Length = 4, CAS Latency = 3)...................................... 22
14.2
Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Autoprecharge) ............ 23
14.3
Interleaved Bank Read (Burst Length = 8, CAS Latency = 3)...................................... 24
14.4
Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Autoprecharge) ............ 25
14.5
Interleaved Bank Write (Burst Length = 8) ................................................................... 26
14.6
Interleaved Bank Write (Burst Length = 8, Autoprecharge).......................................... 27
14.7
Page Mode Read (Burst Length = 4, CAS Latency = 3)............................................... 28
14.8
Page Mode Read / Write (Burst Length = 8, CAS Latency = 3) ................................... 29
14.9
Auto Precharge Read (Burst Length = 4, CAS Latency = 3)........................................ 30
14.10
Auto Precharge Write (Burst Length = 4).................................................................... 31
14.11
Auto Refresh Cycle ..................................................................................................... 32
14.12
Self Refresh Cycle....................................................................................................... 33
14.13
Burst Read and Single Write (Burst Length = 4, CAS Latency = 3)............................ 34
14.14
PowerDown Mode ....................................................................................................... 35
14.15
Autoprecharge Timing (Read Cycle)........................................................................... 36
14.16
Autoprecharge Timing (Write Cycle) ........................................................................... 37
14.17
Timing Chart of Read to Write Cycle........................................................................... 38
14.18
Timing Chart of Write to Read Cycle........................................................................... 38
14.19
Timing Chart of Burst Stop Cycle (Burst Stop Command).......................................... 39
14.20
Timing Chart of Burst Stop Cycle (Precharge Command) .......................................... 39
14.21
CKE/DQM Input Timing (Write Cycle)......................................................................... 40
14.22
CKE/DQM Input Timing (Read Cycle)......................................................................... 41
14.23
Self Refresh/Power Down Mode Exit Timing .............................................................. 42
15.
PACKAGE DIMENSION ........................................................................................................... 43
15.1
54L TSOP (II)-400 mil................................................................................................... 43
16.
REVISION HISTORY ................................................................................................................44
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