參數(shù)資料
型號： VT82C586A
廠商： Electronic Theatre Controls, Inc.
英文描述： PIC Integrated Peripheral Controller
中文描述： 石化整合的周邊控制器
文件頁數(shù)： 40/43頁
文件大?。?/td> 215K
代理商： VT82C586A
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VT82C586A
Preliminary Revision 0.1
October 13, 1996
-
34-
Register Descriptions
Universal Serial Bus Controller Registers (Function 2)
This USB host controller interface is fully compatible with
UHCI specification v1.1. There are two sets of software
accessible registers: PCI configuration registers and USB I/O
registers. The PCI configuration registers are located in the
function 2 PCI configuration space of the VT82C586A. The
USB I/O registers are defined in the UHCI v1.1 specification.
PCI Configuration Space Header
Offset 1-0 - Vendor ID ....................................................... RO
0-7
Vendor ID
................. (1106h = VIA Technologies)
Offset 3-2 - Device ID ......................................................... RO
0-7
Device ID
(3038h = VT82C586A USB Controller)
Offset 5-4 - Command ....................................................... RW
15-8 Reserved
........................................ always reads 0
7
Address Stepping
...................... default=0 (disabled)
6
Reserved
(parity error response)..................fixed at 0
5
Reserved
(VGA palette snoop) ....................fixed at 0
4
Memory Write and Invalidate
. default=0 (disabled)
3
Reserved
(special cycle monitoring)............fixed at 0
2
Bus Master
............................... default=0 (disabled)
1
Memory Space
........................... default=0 (disabled)
0
I/O Space
............................... default=0 (disabled)
Offset 7-6 - Status ........................................................... RWC
15
Reserved
(detected parity error).......... always reads 0
14
Signalled System Error
.............................. default=0
13
Received Master Abort
.............................. default=0
12
Received Target Abort
.............................. default=0
11
Signalled Target Abort
.............................. default=0
10-9 DEVSEL# Timing
00 Fast
01 Medium......................................default (fixed)
10 Slow
11 Reserved
8-0
Reserved
........................................ always reads 0
Offset 8 - Revision ID (nnh) .............................................. RO
7-0
Silicon Revision Code (0 indicates first silicon)
Offset 9 - Programming Interface (00h) .......................... RO
Offset A - Sub Class Code (03h) ....................................... RO
Offset B - Base Class Code (0Ch) ..................................... RO
Offset 0D - Latency Timer ............................................... RW
7-0
Timer Value
default = 16h
Offset 0E - Header Type (00h) ......................................... RO
Offset 23-20 - USB I/O Register Base Address .............. RW
31-16 Reserved
........................................always reads 0
15-5 USB I/O Register Base Address.
Port Address for
the base of the USB I/O Register block,
corresponding to AD[15:5]
4-0
00001b
Offset 3C - Interrupt Line (00h) ..................................... RW
Offset 3D - Interrupt Pin (04h) ....................................... RW
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