參數(shù)資料
型號(hào)： VT82C586A
廠商： Electronic Theatre Controls, Inc.
英文描述： PIC Integrated Peripheral Controller
中文描述： 石化整合的周邊控制器
文件頁數(shù)： 25/43頁
文件大小： 215K
代理商： VT82C586A
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VT82C586A
Preliminary Revision 0.1
October 13, 1996
-
19-
Register Descriptions
DMA Controller I/O Registers
Ports 00-0F - Master DMA Controller
Channels 0-3 of the Master DMA Controller control System
DMA Channels 0-3. There are 16 Master DMA Controller
registers:
I/O Address Bits 15-0
Register Name
0000 0000 000x 0000
Ch 0 Base / Current Address
0000 0000 000x 0001
Ch 0 Base / Current Count
0000 0000 000x 0010
Ch 1 Base / Current Address
0000 0000 000x 0011
Ch 1 Base / Current Count
0000 0000 000x 0100
Ch 2 Base / Current Address
0000 0000 000x 0101
Ch 2 Base / Current Count
0000 0000 000x 0110
Ch 3 Base / Current Address
0000 0000 000x 0111
Ch 3 Base / Current Count
0000 0000 000x 1000
Status / Command
0000 0000 000x 1001
Write Request
0000 0000 000x 1010
Write Single Mask
0000 0000 000x 1011
Write Mode
0000 0000 000x 1100
Clear Byte Pointer F/F
0000 0000 000x 1101
Master Clear
0000 0000 000x 1110
Clear Mask
0000 0000 000x 1111
R/W All Mask Bits
RW
RW
RW
RW
RW
RW
RW
RW
RW
WO
WO
WO
WO
WO
WO
RW
Note that not all bits of the address are decoded.
The Master DMA Controller is compatible with the Intel 8237
DMA Controller chip. Detailed descriptions of 8237 DMA
Controller operation can be obtained from the Intel Peripheral
Components Data Book and numerous other industry
publications.
Ports C0-DF - Slave DMA Controller
Channels 0-3 of the Slave DMA Controller control System
DMA Channels 4-7. There are 16 Slave DMA Controller
registers:
I/O Address Bits 15-0
0000 0000 1100 000x
0000 0000 1100 001x
0000 0000 1100 010x
0000 0000 1100 011x
0000 0000 1100 100x
0000 0000 1100 101x
0000 0000 1100 110x
0000 0000 1100 111x
0000 0000 1101 000x
0000 0000 1101 001x
0000 0000 1101 010x
0000 0000 1101 011x
0000 0000 1101 100x
0000 0000 1101 101x
0000 0000 1101 110x
0000 0000 1101 111x
Register Name
Ch 0 Base / Current Address
Ch 0 Base / Current Count
Ch 1 Base / Current Address
Ch 1 Base / Current Count
Ch 2 Base / Current Address
Ch 2 Base / Current Count
Ch 3 Base / Current Address
Ch 3 Base / Current Count
Status / Command
Write Request
Write Single Mask
Write Mode
Clear Byte Pointer F/F
Master Clear
Clear Mask
Read/Write All Mask Bits
RW
RW
RW
RW
RW
RW
RW
RW
RW
WO
WO
WO
WO
WO
WO
WO
Note that not all bits of the address are decoded.
The Slave DMA Controller is compatible with the Intel 8237
DMA Controller chip. Detailed description of 8237 DMA
controller operation can be obtained from the Intel Peripheral
Components Data Book and numerous other industry
publications.
Ports 80-8F - DMA Page Registers
There are eight DMA Page Registers, one for each DMA
channel. These registers provide bits 16-23 of the 24-bit
address for each DMA channel (bits 0-15 are stored in
registers in the Master and Slave DMA Controllers). They are
located at the following I/O Port addresses:
I/O Address Bits 15-0
Register Name
0000 0000 1000 0111
Channel 0 DMA Page (M-0).........RW
0000 0000 1000 0011
Channel 1 DMA Page (M-1).........RW
0000 0000 1000 0001
Channel 2 DMA Page (M-2).........RW
0000 0000 1000 0010
Channel 3 DMA Page (M-3).........RW
0000 0000 1000 1111
0000 0000 1000 1011
0000 0000 1000 1001
0000 0000 1000 1010
Channel 4 DMA Page (S-0)..........RW
Channel 5 DMA Page (S-1)..........RW
Channel 6 DMA Page (S-2)..........RW
Channel 7 DMA Page (S-3) .........RW
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