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參數(shù)資料
| 型號： | VSC8117QP1 |
| 廠商： | VITESSE SEMICONDUCTOR CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | GIGATRUE 550 CAT6 PATCH 25 FT, SNAGLESS, BLUE |
| 中文描述： | TRANSCEIVER, PQFP64 |
| 封裝： | 10 X 10 MM, HEAT SPREADER, PLASTIC, QFP-64 |
| 文件頁數(shù)： | 4/22頁 |
| 文件大小： | 406K |
| 代理商： | VSC8117QP1 |
VITESSE
Data Sheet
VSC8117
ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux
with Integrated Clock Generation and Clock Recovery
Page 4
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 805/388-3700 FAX: 805/987-5896
G52221-0, Rev 4.1
1/8/00
Loss of Signal
The VSC8117 features Loss of Signal (LOS) detection. Loss of Signal is declared if the incoming serial
data stream has no transition continuously for more than 128 bits. During an LOS condition, the VSC8117
forces the receive data low which is an indication for any downstream equipment that an optical interface failure
has occurred. The receive section continues to be clocked by the CRU as it is now locked to the CRUREFCLK
unless DSBLCRU is active or CRUREFSEL is inactive in which case it will be clocked by the CMU. This LOS
condition will be removed when the part detects more than 16 transitions in a 128 bit time window. This LOS
detection feature can be disabled by applying a high level to the LOSDETEN_ input. The VSC8117 also has a
PECL input LOSPECL to force the part into a Loss of Signal state. Most optics have a PECL output usually
called “SD” or “FLAG” indicating a lack of or presence of optical power. Depending on the optics manufacturer
this signal is either active high or active low. The LOSPECL input on the VSC8117 is active low.
Figure 2: Data and Clock Receive Block Diagram
Facility Loopback
The Facility Loopback function is controlled by the FACLOOP signal. When the FACLOOP signal is set
high, the Facility Loopback mode is activated and the high speed serial receive data (RXDATAIN) is presented
to the high speed transmit output (TXDATAOUT). See Figure 3. In Facility Loopback mode the high speed
receive data (RXDATAIN) is also converted to parallel data and presented to the low speed receive data output
pins (RXOUT[7:0]). The receive clock (RXCLKIN) or the recovered clock is also divided down and presented
to the low speed clock output (RXLSCKOUT).
D Q
D Q
D Q
0
1
Divide-by-8
CMU
D Q
PM5355
D Q
RXOUT[7:0]
FP
RXLSCKOUT
VSC8117
CRU
RXDATAIN+/-
RXCLKIN+/-
DSBLCRU
0
1
0
1
LOSPECL
LOSDETEN_
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相關代理商/技術參數(shù) |
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| VSC8117QP2 | 制造商:VITESSE 制造商全稱:Vitesse Semiconductor Corporation 功能描述:ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery |
| VSC8121 | 制造商:VITESSE 制造商全稱:Vitesse Semiconductor Corporation 功能描述:2.488GHz SONET/SDH Clock Generator |
| VSC8121QI | 制造商:Vitesse Semiconductor Corporation 功能描述: |
| VSC8122 | 制造商:VITESSE 制造商全稱:Vitesse Semiconductor Corporation 功能描述:Multi-Rate SONET/SDH Clock and Data Recovery IC |
| VSC8122QP | 制造商:Vitesse Semiconductor Corporation 功能描述: |
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