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參數(shù)資料
| 型號： | VSC8117QP1 |
| 廠商： | VITESSE SEMICONDUCTOR CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | GIGATRUE 550 CAT6 PATCH 25 FT, SNAGLESS, BLUE |
| 中文描述： | TRANSCEIVER, PQFP64 |
| 封裝： | 10 X 10 MM, HEAT SPREADER, PLASTIC, QFP-64 |
| 文件頁數(shù)： | 10/22頁 |
| 文件大?。?/td> | 406K |
| 代理商： | VSC8117QP1 |
VITESSE
Data Sheet
VSC8117
ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux
with Integrated Clock Generation and Clock Recovery
Page 10
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 805/388-3700 FAX: 805/987-5896
G52221-0, Rev 4.1
1/8/00
Table 4: Transmit Data Input Timing Table (
STS-12 Operation
)
Table 5: Transmit Data Input Timing Table (
STS-3 Operation
)
Note: Duty cycle for TXLSCKOUT is 50% +/- 10% worst case
Figure 10: Receive Data Output Timing Diagram
Table 6: Receive Data Output Timing Table (
STS-12 Operation
)
Parameter
Description
Min
Typ
Max
Units
T
CLKOUT
T
INSU
T
INH
Transmit data output byte clock period
Transmit data setup time with respect to TXLSCKOUT
Transmit data hold time with respect to TXLSCKOUT
-
12.86
-
-
-
-
-
ns
ns
ns
1.0
1.0
Parameter
Description
Min
Typ
Max
Units
T
CLKOUT
T
INSU
T
INH
Transmit data output byte clock period
Transmit data setup time with respect to TXLSCKOUT
Transmit data hold time with respect to TXLSCKOUT
-
51.44
-
-
-
-
-
ns
ns
ns
1.0
1.0
Parameter
Description
Min
Typ
Max
Units
T
RXCLKIN
T
RXLSCK
Receive clock period
Receive data output byte clock period
Time data on RXOUT [7:0] and FP is valid before and
after the rising edge of RXLSCKOUT
Pulse width of frame detection pulse FP
-
-
1.608
12.86
-
-
ns
ns
T
RXVALID
4.0
-
-
ns
T
PW
-
12.86
-
ns
A1
A2
A2
A2
A2
T
RXVALID
T
RXLSCK
T
RXCLKIN
RXOUT [7:0]
RXLSCKOUT
RXCLKIN+
RXCLKIN-
FP
T
RXVALID
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| VSC8117QP2 | 制造商:VITESSE 制造商全稱:Vitesse Semiconductor Corporation 功能描述:ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery |
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