參數(shù)資料
型號： VSC7217
廠商： Vitesse Semiconductor Corporation.
英文描述： Multi-Gigabit Interconnect Chip
中文描述： 千兆位級互連芯片
文件頁數(shù)： 22/36頁
文件大?。?/td> 516K
代理商： VSC7217
VITESSE
Preliminary Datasheet
VSC7217
Mutli-Gigabit Interconnect Chip
Page 22
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 805/388-3700 FAX: 805/987-5896
6/14/00
G52325-0
,
Rev. 3.0
Figure 17: Receive Output Timing Waveforms with
RMODE
= 00 or 01
Table 12: Receive Output AC Characteristics with
RMODE
= 00 or 01
Figure 18: Receive Output Timing Waveforms with
RMODE
= 10 or 11
Table 13: Receive Output AC Characteristics with
RMODE
= 10 or 11
Parameters
Description
Min
Max
Units
Conditions
T
CQ
REFCLK
Rising Edge to TTL
Output Transition
REFCLK
Rising Edge to TTL
Output Transition
TTL Output Transition to
REFCLK
Rising Edge
2.58 ns - 0 bc
5.43 ns - 0 bc
ns
RMODE = 00
bc = Bit Clock
RMODE = 01
bc = Bit Clock
T
CQ
2.58 ns - 2 bc
5.43 ns - 2 bc
ns
T
QC
T
PER
- T
CQ_max
ns
Parameters
Description
Min
Max
Units
Conditions
T
CQ
RCLKn
/
RCLKNn
Rising Edge to
TTL Output Transition
TTL Output Transition to
RCLK n
/
RCLKNn
Rising Edge
RCLKn
/
RCLKNn
Duty Cycle
-1.25 ns + 4 bc
1.25 ns + 4 bc
ns
RMODE
= 10 or 11
bc = Bit Clock
T
CQ
T
PER
- T
CQ_max
T
PER
- T
CQ_min
ns
DC
50% - 1 ns
50% + 1 ns
ns
Measured at 1.4. V
REFCLK
(DUAL = 0)
Rn(7:0) TBERRn
KCHn IDLEn ERRn
PSDETn RSDETn
Valid
Valid
Valid
T
CQ_max
T
CQ_min
REFCLK
(DUAL = 1)
T
QC_min
T
PER
RCLKn
(DUAL = 0)
Rn(7:0) TBERRn
KCHn IDLEn ERRn
PSDETn RSDETn
Valid
Valid
Valid
T
CQ_max
T
CQ_min
RCLKn/RCLKNn
(DUAL = 1)
T
QC_min
T
PER
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