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參數(shù)資料
| 型號： | VSC7217 |
| 廠商： | Vitesse Semiconductor Corporation. |
| 英文描述： | Multi-Gigabit Interconnect Chip |
| 中文描述： | 千兆位級互連芯片 |
| 文件頁數(shù)： | 16/36頁 |
| 文件大?。?/td> | 516K |
| 代理商： | VSC7217 |
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VITESSE
Preliminary Datasheet
VSC7217
Mutli-Gigabit Interconnect Chip
Page 16
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 805/388-3700 FAX: 805/987-5896
6/14/00
G52325-0
,
Rev. 3.0
Loopback Operation
Loopback control pins,
LBENn(1:0)
, are provided in each channel to internally loopback data paths for on-
chip diagnosis. Both serial and parallel loopback functions are provided.
Table 8: Loopback Mode Selection
When
LBENn(1:0)
=10, Serial Loopback mode is selected. The transmitter’s serial transmit data is inter-
nally connected to the receiver’s CRU input. The serial loopback paths are labelled LBTXn in the VSC7217
block diagram on the first page. This allows parallel data on
Tn(7:0)
to be encoded, serialized, looped back,
deserialized and decoded. This mode is intended for the system to verify functionality of the local VSC7217
prior to attempting to establish an external link. The
PTXn
and
RTXn
outputs are unaffected by the state of
LBENn(1:0)
.
When
LBENn(1:0)
=01, Parallel Loopback mode is selected. The
Rn(7:0)
outputs are looped back to the
Tn(7:0)
inputs (see Figure11).
WSENn
does not have a loopback source and is internally connected to a logic
LOW.
K CHAR
does not have a loopback source and is internally connected to a logic HIGH. The
C/Dn
input
is obtained by decoding the link status outputs such that either a data character, special character, or IDLE
(K28.5) is transmitted. When the link is in the LOS or RESYNC states,
C/Dn
is asserted and the data path is set
to 0xBC so that an IDLE will be transmitted. For other link status conditions
C/Dn
follows the
K CHn
status
bit. This guarantees that IDLE and special characters will be correctly looped back along with normal data, and
also has the effect of looping back the data received as a normal data character when a disparity error, out-of-
band character, or underflow/overflow link status condition occurs.
In Parallel Loopback mode, the receiver uses an internal copy of
REFCLK
as the word clock in each
receiver. This data is looped back to the transmitter with
TMODE(2:0)
internally set to 000. This guarantees
that the parallel loopback data to be re-transmitted will be frequency-locked to the transmitter’s
REFCLK
. This
also means that the receiver parallel output data timing will not match the normal system timing that is exter-
nally selected by
RMODE(1:0)
. The parallel output data should be ignored in this mode of operation.
This internal loopback configuration also allows rate matching to be performed in the receivers’ elastic
buffers. Rate matching is controlled and operates exactly the same way that it does in normal mode. This is
required to avoid receiver Overrun/Underrun errors in the loopback device if the remote transmitting device’s
REFCLK
is not frequency-locked to the loopback device’s
REFCLK
. Keep in mind that the
LBENn(1:0)
,
RXP/Rn
,
PTXENn
,
RTXENn
and
BIST
inputs must all be configured appropriately in order for end-to-end
parallel loopback to function correctly in a user environment. Parallel Loopback mode is internally disabled
when BIST mode is enabled.
LBENn(1:0)
Loopback Mode
0 0
0 1
1 0
1 1
Normal Operation
Internal Parallel Loopback
Internal Serial Loopback
Reserved
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