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參數(shù)資料
| 型號： | VSC7217 |
| 廠商： | Vitesse Semiconductor Corporation. |
| 英文描述： | Multi-Gigabit Interconnect Chip |
| 中文描述： | 千兆位級互連芯片 |
| 文件頁數(shù)： | 10/36頁 |
| 文件大?。?/td> | 516K |
| 代理商： | VSC7217 |
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VITESSE
Preliminary Datasheet
VSC7217
Mutli-Gigabit Interconnect Chip
Page 10
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 805/388-3700 FAX: 805/987-5896
6/14/00
G52325-0
,
Rev. 3.0
Figure 7: Receive Timing,
RMODE(1:0)
= 01
Figure 8: Receive Timing,
RMODE(1:0)
= 1X
The data coming from the decoder is clocked into the elastic buffer by the recovered clock from the chan-
nel’s CRU. The data is clocked out of the elastic buffers with word clock. If the transmitting device’s
REFCLK
is not precisely frequency locked to a receive channel’s word clock, then the channel’s elastic buffer will tend to
gradually fill or empty as the recovered clock (which is by definition frequency locked to the transmitter’s
REFCLK
) steadily drifts in phase relative to the word clock.
To accommodate frequency differences between a transmitter’s
REFCL K
and the word clock, the
VSC7217 can automatically perform rate matching by either deleting or duplicating IDLE characters. The
FLOCK
input must be LOW to enable rate matching which, based on how the
WSI
input is connected, can
either be performed in each channel individually or can be performed in parallel across a group of channels that
are word-aligned. This is discussed in detail in the following section describing
Word Alignment
. The user
must ensure that the frequency at which IDLEs are simultaneously transmitted on each channel accommodates
the frequency differences, if any, in their system architecture. Not meeting the IDLE density requirements could
result in Underrun/Overrun Errors.
REFCLK
(DUAL = 0)
IDLEn
KCHn
ERRn
Valid
Valid
Rn(7:0)
REFCLK
(DUAL = 1)
Valid
RCLKn
(DUAL = 0)
Valid
IDLEn
KCHn
ERRn
Valid
Valid
Rn(7:0)
RCLKn
(DUAL = 1)
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