參數(shù)資料
型號(hào)： VSC7216-01
廠商： VITESSE SEMICONDUCTOR CORP
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Multi-Gigabit Interconnect Chip
中文描述： SPECIALTY TELECOM CIRCUIT, PBGA256
封裝： 27 MM, BGA-256
文件頁(yè)數(shù)： 22/38頁(yè)
文件大?。?/td> 561K
代理商： VSC7216-01
VSC7216-01
Multi-Gigabit Interconnect Chip
Multi-Gigabit Interconnect Chip
Preliminary Data Sheet
VITESSE
Page 22
G52352-0, Rev 3.2
05/05/01
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano
Camarillo, CA 93012
Tel: (800) VITESSE
FAX: (805) 987-5896
Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Figure 15: Transmit Input Timing Waveforms with
TMODE
= 11X (
“
ASIC-Friendly
”
Timing)
Table 11: Transmit Input AC Characteristics with
TMODE
= 11X
Figure 16: Transmit Serial Timing Waveforms
Table 12: Transmit Serial AC Characteristics
Parameters
Description
Min
Max
Units
Conditions
T
S
Input Skew relative to the rising
edge of TBCn or TBCA
—
2.0
bc
Measured between the valid data
level of the input and the 1.4V point
of TBCn or TBCA. bc = bit clock.
Parameters
Description
Min
Max
Units
Conditions
T
SDR,
T
SDF
TXn+/- rise and fall time
—
330
ps
Measured between 20% to
80% of the valid data level.
ENDEC=1 TMODE=000
ENDEC=1 TMODE=10X
ENDEC=1 TMODE=101
IEEE 802.3z Clause 38.69,
tested on a sample basis.
IEEE 802.3z Clause 38.69,
tested on a sample basis.
T
LAT
Latency, REFCLK to TX0
Latency, TBCA to TX0
Latency, TBCB/C/D to TX0
Serial data output
Total Jitter (p-p)
Serial data output
Deterministic Jitter (p-p)
22bc+0.1ns
38bc+0.4ns
32bc+0.1ns
22bc+0.7ns
40bc+0.7ns
42bc+0.6ns
bc + ns
T
J
—
192
ps
T
DJ
—
80
ps
Valid
T
S
Valid
Valid
T
S
Internal Clock
(from PLL)
TBCn
(or TBCA)
Tn(7:0)
C/Dn
WSENn
T
SDR,
T
SDF
T
LAT
TXn+, TXn-
TX0
REFCLK
(or TBCn)
相關(guān)PDF資料
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