- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄359429 > VSC7216-01 (VITESSE SEMICONDUCTOR CORP) Multi-Gigabit Interconnect Chip PDF資料下載
參數(shù)資料
| 型號(hào)： | VSC7216-01 |
| 廠商： | VITESSE SEMICONDUCTOR CORP |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Multi-Gigabit Interconnect Chip |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA256 |
| 封裝： | 27 MM, BGA-256 |
| 文件頁數(shù)： | 13/38頁 |
| 文件大?。?/td> | 561K |
| 代理商： | VSC7216-01 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁當(dāng)前第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁
Preliminary Datasheet
VSC7216-01
Multi-Gigabit Interconnect Chip
VITESSE
G52352-0, Rev 3.2
05/05/01
Page 13
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano
Camarillo, CA 93012
Tel: (800) VITESSE
FAX: (805) 987-5896
Email: prodinfo@vitesse.com
Internet: www.vitesse.com
There are four distinct modes of operation defined in Table 7. The first row disables both word alignment
and rate matching. (The fourth and fifth row configurations function identically to the first row.) The second
row configures the channels to operate independently with rate matching. Word alignment is disabled, and
IDLEs will be dropped/duplicated independently in each channel as required. The third row configures the part
to perform word alignment and rate matching. The receive channels will be aligned per the device driving
WSO, and IDLE words will be dropped/duplicated across the aligned channels as required. The last row
configures the part to perform word alignment and disables rate matching. This mode of operation is
appropriate for a frequency-locked application where it desired to align the receive channels without altering
the received data streams.
Using Multiple VSC7216-01s in Parallel
Multiple VSC7216-01s can be used in parallel to form wider bus widths. In order for word alignment to
function correctly across multiple devices, each transmit channel
’
s input data must be transmitted on a common
clock, and each receive channel
’
s output data must also be aligned to a common word clock. This requires that
all transmitting devices use either the same or identical REFCLKs, and that TMODE(2:0)=000 (inputs timed to
REFCLK) or TMODE(2:0)=1X0 (inputs timed to TBCA). If inputs are timed to TBCA, then all transmitting
devices must use either the same or identical TBCAs. Since all receive channels must use a common word
clock, the receiving devices must also use the same or identical REFCLKs and it must be selected as the word
clock for all receive channels (RMODE(1:0)=0X).
If the transmitting devices
’
REFCLKs are not frequency-locked to the receiving devices
’
REFCLKs,
IDLEs will have to be added to or dropped from all the channels at the same time. In order to implement this,
one VSC7216-01 is arbitrarily chosen as the
“
Master
”
and its WSO output is driven to the WSI inputs of all the
receiving VSC7216-01s, including itself. WSO is asserted prior to the VSC7216-01 adding/dropping IDLEs so
all the VSC7216-01s will operate simultaneously. WSO uses a simple 3-bit serial protocol, synchronous to the
Master channel
’
s word clock for indicating the required synchronization action to other VSC7216-01s. A steady
LOW level indicates no action is required.
‘
101
’
indicates that Master Channel A has seen a Word Sync Event.
The relative timing relationship between receiving a Word Sync Event (on all channels together) and seeing
‘
101
’
on the WSI input in the other channels allows these channels to word-synchronize with Master Channel
A.
‘
110
’
indicates that the next IDLE encountered in the receive data stream should be deleted.
‘
111
’
indicates
that an IDLE should be inserted after the next IDLE encountered in the receive data stream. Note that the
arbitrarily chosen Master Channel A must be an active channel.
Decoder Bypass Mode
If ENDEC is LOW, the 8B/10B decoder is bypassed and a 10-bit received character Rn(9:0) is output from
each receive channel. The KCHn output becomes Rn8, and ERRn becomes Rn9. Character alignment is
handled differently in this mode of operation. As mentioned in the
“
Encoder Bypass Mode
”
section, the
KCHAR input becomes ENCDET which enables Comma detection and re-synchronization when HIGH, and
disables re-synchronization when LOW. Only the
‘
0011111xxx
’
version of the
“
Comma
”
pattern is recognized
when ENDEC is LOW. The IDLEn output becomes COMDET (Comma Detect) which signals detection of the
‘
0011111xxx
’
Comma pattern in the current 10-bit output character when HIGH. This mode of operation is
equivalent to a 10-bit interface commonly found in serializer/deserializers for the Fibre Channel (VSC7125)
and Gigabit Ethernet markets (VSC7135).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VSC7216-02 | 740; 38000/740 Series; Microcontroller; Bit Size: 8-bit; ROM: 60K; RAM: 2048; ROM Type: Mask ROM; CPU: 740 core; Minimum Instruction Execution Time (ns): 240 (@16.8MHz); Operating Frequency / Supply Voltage: 1.8 to 5.5V; Operating Ambient Temperature (°C): -20 to 85; Package Code: PLQP0064GA-A (64P6U-A) |
| VSC7217 | Multi-Gigabit Interconnect Chip |
| VSC7226 | 740; 38000/740 Series; Microcontroller; Bit Size: 8-bit; ROM: 60K; RAM: 2048; ROM Type: Mask ROM; CPU: 740 core; Minimum Instruction Execution Time (ns): 240 (@16.8MHz); Operating Frequency / Supply Voltage: 1.8 to 5.5V; Operating Ambient Temperature (°C): -20 to 85; Package Code: PRDP0064BA-A (64P4B) |
| VSC7251 | PCI-Express Serial Attached SCSI Single Chip RAID Controller |
| VSC7280 | 740; 38000/740 Series; Microcontroller; Bit Size: 8-bit; ROM: 60K; RAM: 2048; ROM Type: Mask ROM; CPU: 740 core; Minimum Instruction Execution Time (ns): 240 (@16.8MHz); Operating Frequency / Supply Voltage: 1.8 to 5.5V; Operating Ambient Temperature (°C): -20 to 85; Package Code: PTLG0064JA-A (64F0G) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| VSC7216-02 | 制造商:VITESSE 制造商全稱:Vitesse Semiconductor Corporation 功能描述:02 Low Power Quad 1.25Gb/s Backplane Transceiver |
| VSC7216UC-01 | 制造商:VITESSE 制造商全稱:Vitesse Semiconductor Corporation 功能描述:Multi-Gigabit Interconnect Chip |
| VSC7216UC-02 | 功能描述:IC TXRX BACKPLANE QUAD 256-BGA RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:25 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:4.5 V ~ 5.5 V 安裝類型:通孔 封裝/外殼:16-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:16-PDIP 包裝:管件 |
| VSC7216UC-06 | 功能描述:IC TXRX BACKPLANE QUAD 256-BGA RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:25 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:4.5 V ~ 5.5 V 安裝類型:通孔 封裝/外殼:16-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:16-PDIP 包裝:管件 |
| VSC7216XUC-02 | 功能描述:4/4 Transceiver IEEE 802.3 制造商:microsemi - ent 系列:- 包裝:托盤 零件狀態(tài):過期 類型:收發(fā)器 協(xié)議:IEEE 802.3 驅(qū)動(dòng)器/接收器數(shù):4/4 雙工:* 接收器滯后:* 數(shù)據(jù)速率:* 電壓 - 電源:2.375 V ~ 2.625 V 工作溫度:* 安裝類型:表面貼裝 封裝/外殼:256-BGA 供應(yīng)商器件封裝:* 標(biāo)準(zhǔn)包裝:40 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。