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| 型號： | VPX3224D |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Video Pixel Decoders |
| 中文描述： | 視頻解碼器像素 |
| 文件頁數(shù)： | 18/92頁 |
| 文件大?。?/td> | 672K |
| 代理商： | VPX3224D |
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PRELIMINARY DATA SHEET
VPX 3225D, VPX 3224D
18
Micronas
2.6.1.2. Embedded Reference Headers/ITU-R656
The VPX supports an output format which is designed to
be compliant with the ITU-R656 recommendation. It is
activated by setting Bit[1:0] of FP-RAM 0x150 to 01. The
16-bit video data must be multiplexed to 8 bit at the
double clock frequency (27 MHz) via FP-RAM 0x154, bit
9 set to 1 (see also section 2.6.3.: Output Multiplexer).
In this mode, video samples are in the following order:
Cb, Y, Cr, Y, ...
The data words 0 and 255 are protected
since they are used for identification of reference head-
ers. This is assured by limitation of the video data. Tim-
ing reference codes are inserted into the data stream at
the beginning and the end of each video line in the fol-
lowing way: A ‘Start of active video’-Header (SAV) is in-
serted before the first active video sample. The ‘end of
active video’-code (EAV) is inserted after the last active
video sample. They both contain information about the
field type and field blanking. The data words occurring
during the horizontal blanking interval between EAV and
SAV are filled with 0x10 for luminance and 0x80 for chro-
minance information. Table 2–3 shows the format of the
SAV and EAV header.
Note that the following changes and extensions to the
ITU-R656 standard have been included to support hori-
zontal and vertical scaling, transmission of VBI-data,
etc.:
– Both the length and the number of active video lines
varies with the selected window parameters. For com-
pliance with the ITU-R656 recommendation, a size of
720 samples per line must be selected for each win-
dow. To enable a constant line length even in the case
of different scaling values for the video windows, the
VPX provides a programmable ‘a(chǎn)ctive video’ signal
(see section 2.8.4.).
– During blanked lines, the VACT signal is suppressed.
VBI-lines can be marked as blanked or active, thus al-
lowing the choice of enabled or suppressed VACT dur-
ing the VBI-window. The vertical field blanking flag (V)
in the SAV/EAV header is set to zero in any line with
enabled VACT signal (valid VBI or video lines).
– During blanked lines, SAV/EAV headers can be sup-
pressed in pairs with FP-RAM 0x150, bit9. To assure
vertical sync detection, some SAV/EAV headers are
inserted during field blanking.
– The flags F, V, and H encoded in the SAV/EAV headers
change on SAV. With FP-RAM 0x150, bit10 set to 1,
they change on EAV. The programmed windows, how-
ever, are delayed by one line. Header suppression is
applied for EAV/SAV pairs.
– For data within the VBI-window (e.g. sliced or raw tele-
text data), the user can select between limitation or re-
duction to 7-bit resolution with an additional LSB as-
suring odd parity (0 and 255 never occur). This option
can be selected via FP-RAM 0x150 [range].
– Ancillary data blocks may be longer than 255 bytes (for
raw data) and are transmitted without checksum. The
secondary data ID is used as high byte of the data
count (DC1; see Table 2–5).
– Ancillary data packets must not follow immediately af-
ter EAV or SAV.
– The total number of clock cycles per line, as well as
valid cycles between EAV and SAV may vary.
Table 2–3:
Coding of the SAV/EAV-header
Bit No.
Word
MSB
LSB
7
6
5
4
3
2
1
0
First
1
1
1
1
1
1
1
1
Second
0
0
0
0
0
0
0
0
Third
0
0
0
0
0
0
0
0
Fourth
1
F
V
H
P3
P2
P1
P0
F = 0 during field 1,
V = 0 during active lines
H = 0 in SAV,
F = 1 during field 2
V = 1 during vertical field blanking
H = 1 in EAV
The bits P0, P1, P2, and P3 are protection bits. Their
states are dependent on the states of F, V, and H as
shown in Table 2–4.
Table 2–4:
Coding of the protection bits
Bit No.
Code
(hex)
MSB
LSB
F
V
H
P3
P2
P1
P0
80
1
0
0
0
0
0
0
0
9D
1
0
0
1
1
1
0
1
AB
1
0
1
0
1
0
1
1
B6
1
0
1
1
0
1
1
0
C7
1
1
0
0
0
1
1
1
DA
1
1
0
1
1
0
1
0
EC
1
1
1
0
1
1
0
0
F1
1
1
1
1
0
0
0
1
The VPX also supports the transmission of VBI-data as
vertical ancillary data during blanked lines in the interval
starting with the end of the SAV and terminating with the
beginning of EAV. In this case, an additional header is in-
serted directly before the valid active data. In this mode,
the position of SAV and EAV depends on the settings for
the programmable VACT signal. These parameters will
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PDF描述 |
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| VPX3224E | Video Pixel Decoders |
| VPX322XE | Video Pixel Decoders |
| VQ1000J | N-Channel Enhancement-Mode MOSFET Transistor(最小漏源擊穿電壓60V,夾斷電流0.225A的N溝道增強(qiáng)型MOSFET晶體管) |
| VQ1000J | N-Channel 60-V (D-S) MOSFET |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| VPX3224D-C3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor |
| VPX3224E | 制造商:MICRONAS 制造商全稱:MICRONAS 功能描述:Video Pixel Decoders |
| VPX3225D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video Pixel Decoders |
| VPX3225D-C3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor |
| VPX3225E | 制造商:MICRONAS 制造商全稱:MICRONAS 功能描述:Video Pixel Decoders |
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