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Host communication - I2C control interface
VL6524/VS6524
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Host communication - I2C control interface
The interface used on the VL6524/VS6524 is a subset of the I2C standard. Higher level
protocol adaptations have been made to allow for greater addressing flexibility. This
extended interface is known as the V2W interface.
V2W protocol layer
Protocol
A message contains two or more bytes of data preceded by a START (S) condition and
followed by either a STOP (P) or a repeated START (Sr) condition followed by another
message.
STOP and START conditions can only be generated by a V2W master.
After every byte transferred the receiving device must output an acknowledge bit which tells
the transmitter if the data byte has been successfully received or not.
The first byte of the message is called the device address byte and contains the 7-bit
address of the V2W slave to be addressed plus a read/write bit which defines the direction
of the data flow between the master and the slave.
The meaning of the data bytes that follow device address changes depending whether the
master is writing to or reading from the slave.
Figure 17.
Write message
For the master writing to the slave the device address byte is followed by 2 bytes which
specify the 16-bit internal location (index) for the data write. The next byte of data contains
the value to be written to that register index. If multiple data bytes are written then the
internal register index is automatically incremented after each byte of data transferred. The
master can send data bytes continuously to the slave until the slave fails to provide an
acknowledge or the master terminates the write communication with a STOP condition or
sends a repeated START (Sr).
Figure 18.
Read message
‘0’ (Write)
S
DEV ADDR R/W A
2 Index Bytes
DATA
P
A/A
DATA
A
N Data Byte
A
DATA
From Master to Slave
From Slave to Master
‘1’ (Read)
S
DEV ADDR R/W A
DATA
P
A
DATA
A
1 or more Data Byte
From Master to Slave
From Slave to Master