參數(shù)資料
型號(hào): VL6524
廠商: 意法半導(dǎo)體
英文描述: VGA single-chip camera module
中文描述: 顯卡單芯片相機(jī)模塊
文件頁(yè)數(shù): 18/70頁(yè)
文件大?。?/td> 505K
代理商: VL6524
Output frame size control
VL6524/VS6524
18/70
6
Output frame size control
6.1
Frame format
An output frame consists of a number of active lines and a number of interframe lines. Each
line consists of embedded line codes (if selected), active pixel data and interline blank data.
Note that by default the interline blanking data is notqualified by the PCLK and therefore is
not captured by the host system.
The default 30fps VGA output frame is shown in
Figure 5
.
Figure 5.
VGA 30fps output frame
If embedded codes are enabled then 8 additional clocks are required in every line to qualify
the codes and 8 fewer interline clock are output leaving the total constant at 1460 clocks per
line.
By default the PCLK output does not qualify the line blanking data and so each line contains
only 1280 clocks (or 1288 if embedded codes are enabled).
The values which are output during line and frame blanking are an alternating pattern of
0x10 and 0x80 by default. These values can be changed by writing to the BlankData_MSB
and BlankData_LSB registers in the
Output formatter control
bank.
6.1.1
Cropping module
The VL6524/VS6524 contains a cropping module which can be used to define a window of
interest within the full VGA array size. The user can set a start location and the required
output size.
Figure 6
shows the example with pipe setup bank0.
16 interframe blanking lines(0x10/0x80)
480 lines ACTIVE VIDEO
(640 by 480 pixels)
Line blanking
(0x10/0x80)
1460 PCLKs
37 interframe blanking lines (0x10/0x80)
1280 PCLKs
553 lines
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