
388
SAM G51 [DATASHEET]
11209C–ATARM–20-Dec-13
19.4.3.6
Calibration Bit
Calibration bits do not interfere with the embedded Flash memory plane.
The calibration bits cannot be modified.
The status of calibration bits are returned by the EEFC. The sequence is:
Issue the Get CALIB bit command by writing EEFC_FCR with GCALB (see
Table 19-2). The FARG field is
meaningless.
Calibration bits can be read by the software application in EEFC_FRR. The first word read corresponds to the first
32 calibration bits. The following reads provide the next 32 calibration bits as long as it is meaningful. Extra reads
to EEFC_FRR return 0.
The 8/16/24 MHz fast RC oscillator is calibrated in production. This calibration can be read through the Get CALIB bit
command. The table below shows the bit implementation for each frequency:
The RC calibration for the 8 MHz is set to ‘1000000’.
19.4.3.7
Security Bit Protection
When the security is enabled, access to the Flash, either through the JTAG/SWD interface or through the Fast Flash
Programming interface, is forbidden. This ensures the confidentiality of the code programmed in the Flash.
The security bit is GPNVM0.
Disabling the security bit can only be achieved by asserting the ERASE pin at 1, and after a full Flash erase is performed.
When the security bit is deactivated, all accesses to the Flash are permitted.
19.4.3.8
Unique Identifier
Each part is programmed with a 2 × 512-byte unique identifier. It can be used to generate keys for example. To read the
unique identifier, the sequence is:
Send the Start read unique identifier command (STUI) by writing EEFC_FCR with the STUI command.
When the unique identifier is ready to be read, the FRDY bit in EEFC_FSR falls.
The unique identifier is located at the address 0x00400000-0x004003FF, in the first 128 bits of the Flash memory
mapping.
To stop the unique identifier mode, the user needs to send the Stop read unique identifier command (SPUI) by
writing EEFC_FCR with the SPUI command.
When the SPUI command has been performed, the FRDY bit in EEFC_FSR rises. If an interrupt was enabled by
setting the FRDY bit in EEFC_FMR, the interrupt line of the interrupt controller is activated.
Note that during the sequence, the software cannot run out of Flash.
19.4.3.9
User Signature
Each part contains a user signature of 512 bytes. It can be used for storage. Read, write and erase of this area is
allowed.
To read the user signature, the sequence is as follows:
Send the Start read user signature command (STUS) by writing EEFC_FCR with the STUS command.
When the user signature is ready to be read, the FRDY bit in EEFC_FSR falls.
The user signature is located in the first 512 bytes of the Flash memory mapping, thus, at the address
0x00400000-0x004001FF.
Table 19-5.
Calibration Bit Indexes
RC Calibration Frequency
EEFC_FRR Bits
16 MHz output
[28 - 22]
24 MHz output
[38 - 32]