
Preliminary User’s Manual U16228EJ1V0UD
20
LIST OF FIGURES (5/9)
Figure No.
Title
Page
10-8
Operation in HALT Mode.............................................................................................................................. 240
11-1
Block Diagram of Clock Output/Buzzer Output Controller ............................................................................ 241
11-2
Format of Clock Output Selection Register (CKS)........................................................................................ 243
11-3
Format of Port Mode Register 14 (PM14)..................................................................................................... 244
11-4
Remote Control Output Application Example ............................................................................................... 245
12-1
Block Diagram of A/D Converter .................................................................................................................. 246
12-2
Block Diagram of Power-Fail Detection Function ......................................................................................... 247
12-3
Format of A/D Conversion Register (ADCR) ................................................................................................ 248
12-4
Format of A/D Converter Mode Register (ADM) ........................................................................................... 250
12-5
Timing Chart When Boost Reference Voltage Generator Is Used................................................................ 251
12-6
Format of Analog Input Channel Specification Register (ADS) .................................................................... 252
12-7
Format of Power-Fail Comparison Mode Register (PFM)............................................................................. 253
12-8
Format of Power-Fail Comparison Threshold Register (PFT) ...................................................................... 253
12-9
Basic Operation of A/D Converter ................................................................................................................ 255
12-10 Relationship Between Analog Input Voltage and A/D Conversion Result .................................................... 256
12-11 A/D Conversion Operation............................................................................................................................ 257
12-12 Power-Fail Detection (When PFEN = 1 and PFCM = 0)............................................................................... 258
12-13 Overall Error ................................................................................................................................................. 260
12-14 Quantization Error ........................................................................................................................................ 260
12-15 Zero-Scale Error ........................................................................................................................................... 261
12-16 Full-Scale Error ............................................................................................................................................ 261
12-17 Integral Linearity Error .................................................................................................................................. 261
12-18 Differential Linearity Error............................................................................................................................. 261
12-19 Circuit Configuration of Series Resistor String ............................................................................................. 262
12-20 Storing Conversion Result in ADCR and Timing of Data Read from ADCR ................................................. 263
12-21 Analog Input Pin Connection ........................................................................................................................ 264
12-22 Timing of A/D Conversion End Interrupt Request Generation ...................................................................... 265
12-23 Timing of A/D Converter Sampling and A/D Conversion Start Delay ........................................................... 266
13-1
Block Diagram of Serial Interface UART0 .................................................................................................... 269
13-2
Format of Asynchronous Serial Interface Operation Mode Register 0 (ASIM0) ........................................... 271
13-3
Format of Asynchronous Serial Interface Reception Error Status Register 0 (ASIS0) ................................. 273
13-4
Format of Baud Rate Generator Control Register 0 (BRGC0)...................................................................... 274
13-5
Format of Normal UART Transmit/Receive Data ......................................................................................... 279
13-6
Example of Normal UART Transmit/Receive Data Format........................................................................... 279
13-7
Normal Transmission Completion Interrupt Request Timing ........................................................................ 281