參數(shù)資料
型號(hào): UPD77112GC
廠商: NEC Corp.
元件分類: 數(shù)字信號(hào)處理
英文描述: 16-BIT FIXED-POINT DIGITAL SIGNAL PROCESSORS
中文描述: 16位定點(diǎn)數(shù)字信號(hào)處理器
文件頁數(shù): 42/80頁
文件大?。?/td> 451K
代理商: UPD77112GC
Data Sheet U12801EJ4V0DS00
42
μ
PD77110, 77111, 77112
μ
PD77110
(1)
μ
PD77110 AC Characteristics (Unless otherwise specified, T
A
=
40 to +85
°
C, with IV
DD
and EV
DD
within
recommended operating condition range)
Clock
Timing requirements
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
25
ns
CLKIN cycle time
Note 1
t
cCX
PLL lock range
Note 2
10
×
m
50
×
m
ns
CLKIN high-level width
t
wCXH
12.5
ns
CLKIN low-level width
t
wCXL
12.5
ns
CLKIN rise/fall time
t
rfCX
5
ns
Internal clock cycle time
requirements
Note 3
t
cC (R)
15.3
ns
Notes 1.
m: Multiple
2.
This is the range in which the PLL is locked (stably oscillates). Input t
cCX
within this range.
3.
Input t
cCX
so that the value of (t
cCX
÷
m) satisfies this condition.
Timing requirements (T
A
=
40 to +60
°
C, IV
DD
= 2.5 to 2.7 V, EV
DD
= 2.7 to 3.6 V)
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
25
ns
CLKIN cycle time
Note 1
t
cCX
PLL lock range
Note 2
10
×
m
50
×
m
ns
CLKIN high-level width
t
wCXH
12.5
ns
CLKIN low-level width
t
wCXL
12.5
ns
CLKIN rise/fall time
t
rfCX
5
ns
Internal clock cycle time
requirements
Note 2
t
cC (R)
13.3
ns
Notes 1.
m: Multiple
2.
This is the range in which the PLL is locked (stably oscillates). Input t
cCX
within this range.
3.
Input t
cCX
so that the value of (t
cCX
÷
m) satisfies this condition.
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