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參數(shù)資料
| 型號： | UPD77111GK |
| 廠商： | NEC Corp. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 16-BIT FIXED-POINT DIGITAL SIGNAL PROCESSORS |
| 中文描述： | 16位定點數(shù)字信號處理器 |
| 文件頁數(shù)： | 32/80頁 |
| 文件大?。?/td> | 451K |
| 代理商： | UPD77111GK |
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Data Sheet U12801EJ4V0DS00
32
μ
PD77110, 77111, 77112
8.3.1 Settings related to clock control
External pins PLL0 through PLL2 are used to set the multiple of the PLL. PLL0 and PLL1 are multiplexed with
general-purpose I/O ports P2 and P3, and can be used as PLL setting pins only when it is so specified.
The multiple must be an integer from 1 to 8.
<PLL2: PLL1: PLL0> 000 m = 1
001 m = 2
:
111 m = 8
The output division ratio is fixed to 1/1 and the halt division ratio is fixed to 1/8.
Where the PLL multiple is m, the relationship between each operation mode and operating clock is as follows:
Operation Mode
Clock Supplied to DSP
Normal operation mode
m times external input clock
HALT mode
m/8 times external input clock
STOP mode
Stopped
For details on how to set the PLL multiple, refer to
4.2 Initializing PLL
. Because the setting of PLL0 through
PLL2 becomes valid in the PLL initialization mode, the value of PLL0 through PLL2 must be fixed before the PLL
initialization mode is set.
The option that makes CLKOUT pin output valid or invalid is fixed to “valid”.
8.3.2 WAKEUP function
The WAKEUP function of the
μ
PD77110 is fixed to “valid”.
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