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參數(shù)資料
| 型號： | uPD72107GC-3B9 |
| 廠商： | NEC Corp. |
| 英文描述： | LAP-B CONTROLLER(Link Access Procedure Balanced mode) |
| 中文描述： | 鱲- B控制器（鏈路訪問過程平衡模式） |
| 文件頁數(shù)： | 6/32頁 |
| 文件大小： | 182K |
| 代理商： | UPD72107GC-3B9 |
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6
μ
PD72107
1. PINS
1.1 Pin Functions
SDIP
QFP
QFJ
Active
Pin No.
Pin No.
Pin No.
Level
V
CC
47
68
50
–
–
+5 V power supply
70
51
GND
14
27
15
–
–
Ground (0 V)
51
28
16
Note that there is more than one ground pin.
74
55
CLK
13
26
14
I
–
System clock input
(Clock)
Input clock of 1 MHz to 8.2 MHz.
RESET
8
22
10
I
L
Initializes the internal
μ
PD72107. Active width of
(Reset)
more than 7 CLK clock cycles is required (clock
input is required).
After reset, this pin becomes a bus slave.
PU
12
25
13
I
–
Pull up to high level when using in normal operation.
(Pull Up)
CS
48
71
52
I
L
When bus master
(Chip Select)
Set to disable.
When bus slave
Read/write operation from the host processor at low
level is enabled.
MRD
52
75
56
O
L
When bus master
(Memory Read)
3-state
Reads the data of the external memory at low level.
When bus slave
High impedance
MWR
53
76
57
O
L
When bus master
(Memory Write)
3-state
Writes the data to the external memory at low level.
When bus slave
High impedance
IORD
49
72
53
I
L
This pin is used when the external host processor
(I/O Read)
reads the contents of the internal registers of the
μ
PD72107.
IOWR
50
73
54
I
L
This pin is used when the external host processor
(I/O Write)
writes the data to the internal registers of the
μ
PD72107.
ASTB
60
5
64
O
H
This pin is used to latch the address output from
(Address Strobe)
the
μ
PD72107 externally.
I/O
Pin Name
Function
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