參數(shù)資料
型號(hào): uPD72107GC-3B9
廠商: NEC Corp.
英文描述: LAP-B CONTROLLER(Link Access Procedure Balanced mode)
中文描述: 鱲- B控制器(鏈路訪問過程平衡模式)
文件頁數(shù): 2/32頁
文件大小: 182K
代理商: UPD72107GC-3B9
2
μ
PD72107
BLOCK DIAGRAM
Name
Function
Bus interface
An interface between the
μ
PD72107 and external memory or external host processor
Internal controller
Manages LAP-B protocol including control of the DMAC block, transmitter block, and receiver block
DMAC
(Direct Memory
Access Controller)
Controls the transfer of data on the external memory to the internal controller or transmitter block,
and controls the writing of data in the internal controller or receiver block to the external memory
TxFIFO
A 16-byte buffer for when transmit data is sent from the DMAC to the transmitter block
RxFIFO
A 32-byte buffer for when receive data is sent from the receiver block to the DMAC
Transmitter
Converts the contents of TxFIFO into an HDLC frame and transmits it as serial data
Receiver
Receives HDLC frame and writes internal data to RxFIFO
Internal bus
An 8-bit address bus and 8-bit data bus that connect the internal controller, DMAC, FIFO, serial block,
and bus interface block
D0-D7
A16D8
-A23D15
A0-A15
IORD
IOWR
MRD
MWR
UBE
CS
ASTB
AEN
READY
HLDRQ
HLDAK
CRQ
INT
CLRINT
B/W
PU
V
CC
GND
RESET
CLK
Bus
interface
Internal controller
TxFIFO
Transmitter
Internal bus
Receiver
RxFIFO
DMAC
TxC
TxD
RTS
CTS
CD
RxC
RxD
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