參數(shù)資料
型號: UPD44324182F5-E37-EQ2-A
廠商: NEC Corp.
元件分類: DRAM
英文描述: 36M-BIT DDRII SRAM 2-WORD BURST OPERATION
中文描述: 36M條位SRAM的2條DDRII字爆發(fā)運作
文件頁數(shù): 19/40頁
文件大?。?/td> 361K
代理商: UPD44324182F5-E37-EQ2-A
19
Data Sheet M16780EJ3V0DS
μ
PD44324082, 44324092, 44324182, 44324362
Notes 1.
When debugging the system or board, these products can operate at a clock frequency slower than TKHKH
(MAX.) without the DLL circuit being used, if DLL# = L. The AC/DC characteristics cannot be guaranteed,
however.
2.
Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge. TKC var
(MAX.) indicates a peak-to-peak value.
3.
V
DD
slew rate must be less than 0.1 V DC per 50 ns for DLL lock retention.
DLL lock time begins once V
DD
and input clock are stable.
4.
Echo clock is very tightly controlled to data valid / data hold. By design, there is a
±
0.1 ns variation from
It is recommended that the device is kept NOP (LD# = H) during these cycles.
echo clock to data. The data sheet parameters reflect tester guardbands and test setup variations.
5.
This is a synchronous device. All addresses, data and control lines must meet the specified setup
and hold times for all latching clock edges.
Remarks 1.
This parameter is sampled.
2.
Test conditions as specified with the output loading as shown in AC Test Conditions
unless otherwise noted.
3.
Control input signals may not be operated with pulse widths less than TKHKL (MIN.).
4.
If C, C# are tied HIGH, K, K# become the references for C, C# timing parameters.
5.
V
DD
Q is 1.5 V DC.
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UPD44324182F5-E40-EQ2-A 36M-BIT DDRII SRAM 2-WORD BURST OPERATION
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