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參數資料
| 型號： | UPD44165094AF5-E40Y-EQ2 |
| 元件分類： | SRAM |
| 英文描述： | 2M X 9 QDR SRAM, 0.45 ns, PBGA165 |
| 封裝： | 13 X 15 MM, PLASTIC, BGA-165 |
| 文件頁數： | 18/40頁 |
| 文件大?。?/td> | 388K |
| 代理商： | UPD44165094AF5-E40Y-EQ2 |
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25
Data Sheet
M17771EJ3V0DS
μPD44165084A, 44165094A, 44165184A, 44165364A
JTAG Specification
These products support a limited set of JTAG functions as in IEEE standard 1149.1.
Test Access Port (TAP) Pins
Pin name
Pin assignments
Description
TCK
2R
Test Clock Input. All input are captured on the rising edge of TCK and all outputs
propagate from the falling edge of TCK.
TMS
10R
Test Mode Select. This is the command input for the TAP controller state machine.
TDI
11R
Test Data Input. This is the input side of the serial registers placed between TDI and
TDO. The register placed between TDI and TDO is determined by the state of the TAP
controller state machine and the instruction that is currently loaded in the TAP instruction.
TDO
1R
Test Data Output. This is the output side of the serial registers placed between TDI and
TDO. Output changes in response to the falling edge of TCK.
Remark The device does not have TRST (TAP reset). The Test-Logic Reset state is entered while TMS is held HIGH
for five rising edges of TCK. The TAP controller state is also reset on the SRAM POWER-UP.
JTAG DC Characteristics (VDD = 1.8 ± 0.1 V, unless otherwise noted)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
JTAG Input leakage current
ILI
0 V
≤ VIN ≤ VDD
–5.0
–
+5.0
μA
JTAG I/O leakage current
ILO
0 V
≤ VIN ≤ VDDQ ,
–5.0
–
+5.0
μA
Outputs disabled
JTAG input HIGH voltage
VIH
1.3
–
VDD+0.3
V
JTAG input LOW voltage
VIL
–0.3
–
+0.5
V
JTAG output HIGH voltage
VOH1
| IOHC | = 100
μA
1.6
–
V
VOH2
| IOHT | = 2 mA
1.4
–
V
JTAG output LOW voltage
VOL1
IOLC = 100
μA
–
0.2
V
VOL2
IOLT = 2 mA
–
0.4
V
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相關代理商/技術參數 |
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|---|---|
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