參數(shù)資料
型號(hào)： UPD44165094AF5-E40Y-EQ2
元件分類(lèi)： SRAM
英文描述： 2M X 9 QDR SRAM, 0.45 ns, PBGA165
封裝： 13 X 15 MM, PLASTIC, BGA-165
文件頁(yè)數(shù)： 1/40頁(yè)
文件大?。?/td> 388K
代理商： UPD44165094AF5-E40Y-EQ2
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
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2006
MOS INTEGRATED CIRCUIT
μPD44165084A, 44165094A, 44165184A, 44165364A
18M-BIT QDRTMII SRAM
4-WORD BURST OPERATION
Document No. M17771EJ3V0DS00 (3rd edition)
Date Published February 2007 NS CP(N)
Printed in Japan
DATA SHEET
The mark <R> shows major revised points.
The revised points can be easily searched by copying an "<R>" in the PDF file and specifying it in the "Find what:" field.
Description
The
μPD44165084A is a 2,097,152-word by 8-bit, the μPD44165094A is a 2,097,152-word by 9-bit, the μPD44165184A
is a 1,048,576-word by 18-bit and the
μPD44165364A is a 524,288-word by 36-bit synchronous quad data rate static RAM
fabricated with advanced CMOS technology using full CMOS six-transistor memory cell.
The
μPD44165084A, μPD44165094A, μPD44165184A and μPD44165364A integrate unique synchronous
peripheral circuitry and a burst counter. All input registers controlled by an input clock pair (K and K#) are latched on
the positive edge of K and K#.
These products are suitable for application which require synchronous operation, high speed, low voltage, high density
and wide bit configuration.
These products are packaged in 165-pin PLASTIC BGA.
Features
1.8 ± 0.1 V power supply
165-pin PLASTIC BGA (13 x 15)
HSTL interface
PLL circuitry for wide output data valid window and future frequency scaling
Separate independent read and write data ports with concurrent transactions
100% bus utilization DDR READ and WRITE operation
Four-tick burst for reduced address frequency
Two input clocks (K and K#) for precise DDR timing at clock rising edges only
Two output clocks (C and C#) for precise flight time
and clock skew matching-clock and data delivered together to receiving device
Internally self-timed write control
Clock-stop capability. Normal operation is restored in 1,024 cycles after clock is resumed.
User programmable impedance output
Fast clock cycle time : 3.3 ns (300 MHz) , 3.7 ns (270 MHz) , 4.0 ns (250 MHz) , 5.0 ns (200 MHz)
Simple control logic for easy depth expansion
JTAG boundary scan
Operating ambient temperature : Commercial TA = 0 to +70°C (-E33, -E40, -E50)
Industrial
TA = –40 to +85
°C (-E37Y, -E40Y, -E50Y)
<R>
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
UPD44165094BF5-E40-EQ3-A 制造商:Renesas Electronics Corporation 功能描述:SRAM Chip Sync Dual 1.8V 18M-Bit 2M x 9-Bit 0.45ns 165-Pin BGA
UPD44165362BF5-E40-EQ3 制造商:Renesas Electronics Corporation 功能描述:UPD44165362BF5-E40-EQ3 - Trays
UPD44165362BF5-E40-EQ3-A 制造商:Renesas Electronics Corporation 功能描述:SRAM Chip Sync Dual 1.8V 18M-Bit 512K x 36 0.45ns 165-Pin BGA
UPD44321182GF-A50(A) 制造商:Renesas Electronics Corporation 功能描述:
UPD44324182BF5-E40-FQ1-A 制造商:Renesas Electronics Corporation 功能描述:RENUPD44324182BF5-E40-FQ1-A 36M-BIT(2M-W
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