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參數(shù)資料
| 型號(hào)： | UPD44164362F5-E50-EQ1 |
| 廠商： | NEC Corp. |
| 英文描述： | 18M-BIT DDRII SRAM 2-WORD BURST OPERATION |
| 中文描述： | 1800萬位的SRAM 2條DDRII字爆發(fā)運(yùn)作 |
| 文件頁數(shù)： | 20/32頁 |
| 文件大?。?/td> | 282K |
| 代理商： | UPD44164362F5-E50-EQ1 |
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Data Sheet M15821EJ7V2DS
μ
PD44164082, 44164182, 44164362
Scan Register Definition (1)
Register name
Description
Instruction register
The instruction register holds the instructions that are executed by the TAP controller when it is
moved into the run-test/idle or the various data register state. The register can be loaded when it is
placed between the TDI and TDO pins. The instruction register is automatically preloaded with the
IDCODE instruction at power-up whenever the controller is placed in test-logic-reset state.
Bypass register
The bypass register is a single bit register that can be placed between TDI and TDO. It allows serial
test data to be passed through the RAMs TAP to another device in the scan chain with as little delay
as possible.
ID register
The ID Register is a 32 bit register that is loaded with a device and vendor specific 32 bit code when
the controller is put in capture-DR state with the IDCODE command loaded in the instruction register.
The register is then placed between the TDI and TDO pins when the controller is moved into shift-DR
state.
Boundary register
The boundary register, under the control of the TAP controller, is loaded with the contents of the
RAMs I/O ring when the controller is in capture-DR state and then is placed between the TDI and
TDO pins when the controller is moved to shift-DR state. Several TAP instructions can be used to
activate the boundary register.
The Scan Exit Order tables describe which device bump connects to each boundary register
location. The first column defines the bit’s position in the boundary register. The second column is
the name of the input or I/O at the bump and the third column is the bump number.
Scan Register Definition (2)
Register name
Bit size
Unit
Instruction register
3
bit
Bypass register
1
bit
ID register
32
bit
Boundary register
107
bit
ID Register Definition
Part number
Organization ID [31:28] vendor revision no.
ID [27:12] part no.
ID [11:1] vendor ID no.
ID [0] fix bit
μ
PD44164082
2M x 8
XXXX
0000 0000 0001 0010
00000010000
1
μ
PD44164182
1M x 18
XXXX
0000 0000 0001 0011
00000010000
1
μ
PD44164362
512K x 36
XXXX
0000 0000 0001 0100
00000010000
1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| UPD44164082F5-E60-EQ1 | 18M-BIT DDRII SRAM 2-WORD BURST OPERATION |
| UPD44164182F5-E60-EQ1 | 18M-BIT DDRII SRAM 2-WORD BURST OPERATION |
| UPD44324184F5-E50-EQ2 | 36M-BIT DDRII SRAM 4-WORD BURST OPERAT |
| UPD444004LLE-A10 | 4M-BIT CMOS FAST SRAM 1M-WORD BY 4-BIT |
| UPD444004LLE-A12 | 4M-BIT CMOS FAST SRAM 1M-WORD BY 4-BIT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UPD44164362F5-E60-EQ1ES | 制造商:NEC Electronics Corporation 功能描述: |
| UPD44165092BF5-E40-EQ3-A | 制造商:Renesas Electronics Corporation 功能描述:2MX9, 2BURST, 250 MHZ QDRII SRAM - Trays |
| UPD44165094BF5-E40-EQ3-A | 制造商:Renesas Electronics Corporation 功能描述:SRAM Chip Sync Dual 1.8V 18M-Bit 2M x 9-Bit 0.45ns 165-Pin BGA |
| UPD44165362BF5-E40-EQ3 | 制造商:Renesas Electronics Corporation 功能描述:UPD44165362BF5-E40-EQ3 - Trays |
| UPD44165362BF5-E40-EQ3-A | 制造商:Renesas Electronics Corporation 功能描述:SRAM Chip Sync Dual 1.8V 18M-Bit 512K x 36 0.45ns 165-Pin BGA |
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