- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383981 > UPD44164362F5-E50-EQ1 (NEC Corp.) 18M-BIT DDRII SRAM 2-WORD BURST OPERATION PDF資料下載
參數(shù)資料
| 型號： | UPD44164362F5-E50-EQ1 |
| 廠商： | NEC Corp. |
| 英文描述： | 18M-BIT DDRII SRAM 2-WORD BURST OPERATION |
| 中文描述： | 1800萬位的SRAM 2條DDRII字爆發(fā)運作 |
| 文件頁數(shù)： | 15/32頁 |
| 文件大小： | 282K |
| 代理商： | UPD44164362F5-E50-EQ1 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁當前第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁
15
Data Sheet M15821EJ7V2DS
μ
PD44164082, 44164182, 44164362
Notes 1.
The device will operate at clock frequencies slower than TKHKH(MAX.).
2.
Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
3.
V
DD
slew rate must be less than 0.1 V DC per 50 ns for DLL lock retention.
DLL lock time begins once V
DD
and input clock are stable.
It is recommended that the device is kept inactive during these cycles.
4.
Echo clock is very tightly controlled to data valid / data hold. By design, there is a
±
0.1 ns variation from
echo clock to data. The data sheet parameters reflect tester guardbands and test setup variations.
5.
This is a synchronous device. All addresses, data and control lines must meet the specified setup
and hold times for all latching clock edges.
Remarks 1.
This parameter is sampled.
2.
Test conditions as specified with the output loading as shown in AC Test Conditions
unless otherwise noted.
3.
Control input signals may not be operated with pulse widths less than TKHKL (MIN.).
4.
If C, /C are tied HIGH, K, /K become the references for C, /C timing parameters.
5.
V
DD
Q is 1.5 V DC.
相關PDF資料 |
PDF描述 |
|---|---|
| UPD44164082F5-E60-EQ1 | 18M-BIT DDRII SRAM 2-WORD BURST OPERATION |
| UPD44164182F5-E60-EQ1 | 18M-BIT DDRII SRAM 2-WORD BURST OPERATION |
| UPD44324184F5-E50-EQ2 | 36M-BIT DDRII SRAM 4-WORD BURST OPERAT |
| UPD444004LLE-A10 | 4M-BIT CMOS FAST SRAM 1M-WORD BY 4-BIT |
| UPD444004LLE-A12 | 4M-BIT CMOS FAST SRAM 1M-WORD BY 4-BIT |
相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UPD44164362F5-E60-EQ1ES | 制造商:NEC Electronics Corporation 功能描述: |
| UPD44165092BF5-E40-EQ3-A | 制造商:Renesas Electronics Corporation 功能描述:2MX9, 2BURST, 250 MHZ QDRII SRAM - Trays |
| UPD44165094BF5-E40-EQ3-A | 制造商:Renesas Electronics Corporation 功能描述:SRAM Chip Sync Dual 1.8V 18M-Bit 2M x 9-Bit 0.45ns 165-Pin BGA |
| UPD44165362BF5-E40-EQ3 | 制造商:Renesas Electronics Corporation 功能描述:UPD44165362BF5-E40-EQ3 - Trays |
| UPD44165362BF5-E40-EQ3-A | 制造商:Renesas Electronics Corporation 功能描述:SRAM Chip Sync Dual 1.8V 18M-Bit 512K x 36 0.45ns 165-Pin BGA |
發(fā)布緊急采購，3分鐘左右您將得到回復。