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Data Sheet S15726EJ2V0DS
63
μ
PD161401
6. COMMANDS
The
μ
PD161401 identifies data bus signals by a combination of the RS, /RD (E), and /WR (R,/W) signals. It interprets
and executes commands only in accordance with the internal timing, without being dependent upon the external clock.
Therefore, the processing speed is extremely high and, usually, no busy check is necessary.
An i80 system CPU interface inputs a low pulse to the /RD pin when it reads data from the
μ
PD161401 to issue a
command. It inputs a low pulse to the /WR pin when it writes data to the
μ
PD161401.
Data can be read from an M68 system CPU interface if a high-pulse signal is input to the R,/W pin, and written if a
low-pulse signal is input to the R,/W pin. A command is executed if a high-pulse signal is input to the E pin in this status.
Therefore, in the explanation of the commands and display commands in
6.1 Control Register 1 (R0)
and the sections
that follow, the M68 system CPU interface uses H, instead of /RD (E), when reading status or display data. This is how
it differs from the i80 system CPU interface.
The commands of the
μ
PD161401 are explained below, taking an i80 system CPU interface as an example. When the
serial interface is used, sequentially input data to the
μ
PD161401, starting from D
7
.
The data bus length to input commands is as follows:
Commands other than those that manipulate the display memory access register (R12) are input in byte units,
regardless of the value of BMOD (control register 2 (R1), bus length setting).
The commands that manipulate the display memory access register (R12) are input in 1-byte units when BMOD = 1,
or in 2-byte units when BMOD = 0.
A. Commands other than those that manipulate display memory access register (R12)
BMOD = 1 (8-bit data bus)
Pin
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
DATA
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
BMOD = 0 (16-bit data bus)
Pin
D
15
D
14
D
13
D
12
D
11
D
10
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
DATA
Note
Note
Note
Note
Note
Note
Note
Note
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Note
0 or 1
B. Display memory access register (R12)
BMOD = 1 (8-bit data bus)
Pin
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
DATA
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
BMOD = 0 (16-bit data bus)
Pin
D
15
D
14
D
13
D
12
D
11
D
10
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
DATA
D
15
D
14
D
13
D
12
D
11
D
10
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0