參數資料
型號: UPD161401P
廠商: NEC Corp.
英文描述: CABLE ASSEMBLY; N MALE TO TNC MALE; 50 OHM, RG214/U COAX, DOUBLE SHIELDED; 12" CABLE LENGTH
中文描述: 256色,1/80-DUTY LCD控制器/驅動器,片內RAM
文件頁數: 35/124頁
文件大?。?/td> 647K
代理商: UPD161401P
Data Sheet S15726EJ2V0DS
35
μ
PD161401
5.5 Display Timing Generator
The display timing generator generates timing signals for the line address circuit and display data latch circuit, from
the display clock. The display data is latched to the display data latch circuit in synchronization with the display clock
and output to the segment driver output pins. The display data can be read completely independently of the access to
the display data RAM by the CPU. Therefore, even if the display data RAM is asynchronously accessed, no adverse
effect, such as flickering, occurs on the LCD.
The internal common timing, LCD AC signal (FR), and frame synchronization signal (FR
SYNC
) are generated by the
display clock. A driver waveform in the frame AC driving mode shown in
Figure 5
14
is generated for the LCD driver
circuit.
When the
μ
PD161401 is used in a multi-chip configuration, the display timing signals for the slave chip (FR and
FR
SYNC
) must be supplied from the master chip.
Table 5
11. Relationship between FR, FR
SYNC
, and Operation Mode
Operation Mode
FR
FR
SYNC
Master (M,/S = H)
Output
Output
Slave (M,/S = L)
Input
Input
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