參數(shù)資料
型號： UPD161401P
廠商： NEC Corp.
英文描述： CABLE ASSEMBLY; N MALE TO TNC MALE; 50 OHM, RG214/U COAX, DOUBLE SHIELDED; 12" CABLE LENGTH
中文描述： 256色，1/80-DUTY LCD控制器/驅(qū)動器，片內(nèi)RAM
文件頁數(shù)： 30/124頁
文件大小： 647K
代理商： UPD161401P
Data Sheet S15726EJ2V0DS
30
μ
PD161401
5.3
Screen Processing
5.3.1
The
μ
PD161401 can blink or reverse a specific area of the full-dot display. Blinking is to turn ON/OFF display
repeatedly at about 1 Hz (complementary color or specified color can be selected) and reversing is to reverse the
grayscale data on the display.
The area to be blinked is specified by using the complementary color/specified color blink start/end line address
registers (R39, R40, R43, and R44), complementary color/specified color blink X address registers (R38, R42), and
complementary color/specified color blink data memory registers (R41, R45).
First, select a blink display start line address and end line address by using the start/end line address registers. Next,
select the column to be blinked by using the blink X address register and blink data memory register.
The specified color blink is blinked between the graphic data and the color data specified by the specified color setting
register (R46).
To select an area to be reversed, use the reverse start/end line address registers (R48, R49), reverse X address
register (R47), and reverse data memory access register (R50).
First, select line addresses at which reverse display is started and stopped, by using the reverse start/end line address
registers. Next, select a column to be reversed, by using the reverse X address register and reverse data memory
access register. The specified blink/reverse X address is incremented by one each time blink/reverse data has been
input.
The complementary color/specified color blink RAM and reverse RAM store the data to be blinked and reversed.
Each RAM is configured of 101 bits (12
×
8 + 5 bits).
To access a desired bit, specify an X address. Blink/reverse data D
0
to D
7
transmitted from the CPU corresponds to
SEG
X
on the LCD, as illustrated in
Figure 5
8
.
If the BLD bit and INV bit of the blink/reverse setting register (R37) are set to H after an area and data have been set,
blinking or reversing the data is started.
Figure 5
9
shows the relationship between the start line address, end line
address, blinking/reversing data, and LCD.
If the same area is specified for complementary color blinking and specified color blinking, the specified color blinking
takes precedence.
Blink/reverse display circuit
Table 5
9. Reversing Operation and Display
Original Grayscale
After Reversing (supplement color)
R/G display data
0, 0, 0
1, 1, 1
0, 0, 1
1, 1, 0
0, 1, 0
1, 0, 1
0, 1, 1
1, 0, 0
1, 0, 0
0, 1, 1
1, 0, 1
0, 1, 0
1, 1, 0
0, 0, 1
1, 1, 1
0, 0, 0
B display data
0, 0
1, 1
0, 1
1, 0
1, 0
0, 1
1, 1
0, 0
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