參數(shù)資料
型號: UDA1380
英文描述: Stereo audio coder-decoder for MD, CD and MP3
中文描述: 立體聲音頻編碼器,可用于MD,CD和MP3解碼器
文件頁數(shù): 31/68頁
文件大?。?/td> 278K
代理商: UDA1380
2002 Sep 16
31
Philips Semiconductors
Product specification
Stereo audio coder-decoder
for MD, CD and MP3
UDA1380
Table 19
Dividers for system clock input
Table 20
WSPLL settings
4
DAC_CLK
DAC clock select.
A 1-bit signal to select the clocks for the DAC
(interpolator and FSDAC analog block). In both cases the clocks must be
128f
s
and 256f
s
(for the analog part), but in one case the clock is derived from
the WSI clock, and in the other case the clock is derived from the SYSCLK.
When this bit is logic 0: SYSCLK is used. When this bit is logic 1: WSPLL is
used. Default value 0.
Dividers for system clock input.
A 2-bit value to select the proper division
factor for the SYSCLK input in such a way that a128f
s
clock will be generated
from the SYSCLK clock signal. The 128f
s
clock is needed for clocking the
decimator and interpolator. Default value 00, see Table 19.
WSPLL setting.
A 2-bit value to select the WSPLL input frequency range.
These set the proper divider setting for the WSPLL. The input is the
WSI signal, the output inside the IC is a 128f
s
and a 256f
s
clock. Default
value 10, see Table 20.
3 and 2
sys_div[1:0]
1 and 0
PLL[1:0]
sys_div1
sys_div0
INPUT CLOCK ON PIN SYSCLK
0
0
1
1
0
1
0
1
256f
s
(default)
384f
s
512f
s
768f
s
PLL1
PLL0
INPUT FREQUENCY RANGE (kHz) ON PIN WSI
0
0
1
1
0
1
0
1
6.25 to 12.5
12.5 to 25
25 to 50 (default)
50 to 100
BIT
SYMBOL
DESCRIPTION
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