參數(shù)資料
型號: UDA1380
英文描述: Stereo audio coder-decoder for MD, CD and MP3
中文描述: 立體聲音頻編碼器,可用于MD,CD和MP3解碼器
文件頁數(shù): 34/68頁
文件大小: 278K
代理商: UDA1380
2002 Sep 16
34
Philips Semiconductors
Product specification
Stereo audio coder-decoder
for MD, CD and MP3
UDA1380
8
PON_BIAS
Power-on BIAS.
A 1-bit value to set the power control setting of the ADC, AVC
and FSDAC. When this bit is logic 0: ADC, AVC and FSDAC bias circuits are
powered-off; when this bit is logic 1: Power-on bias for ADC, AVC and FSDAC.
Default value 0.
Enable control AVC.
A 1-bit value to enable or disable the analog mixer. When
this bit is logic 0: analog mixer is disabled; when this bit is logic 1: analog mixer
is enabled. Default value 0.
Power-on AVC.
A 1-bit value to have power-on control for the analog mixer.
When this bit is logic 0: analog mixer powered-off; when this bit is logic 1:
analog mixer powered-on. Default value 0.
default value 0
Power-on LNA.
A 1-bit value to power-on the LNA and SDC. When this bit is
logic 0: LNA and SDC are powered-off; when this bit is logic 1: LNA and SDC
are powered-on. Default value 0.
Power-on PGAL.
A 1-bit value to have power-on control for the PGA left.
When this bit is logic 0: left PGA is powered-off; when this bit is logic 1: left
PGA is powered-on. Default value 0.
Power-on ADCL.
A 1-bit value to have power-on control for the ADC left.
When this bit is logic 0: left ADC is powered-off; when this bit is logic 1: left
ADC is powered-on. Default value 0.
Power-on PGAR.
A 1-bit value to have power-on control for the PGA right.
When this bit is logic 0: right PGA is powered-off; when this bit is logic 1: right
PGA is powered-on. Default value 0.
Power-on ADCR.
A 1-bit value to have power-on control for the ADC right.
When this bit is logic 0: right ADC is powered-off; when this bit is logic 1: right
ADC is powered-on. Default value 0.
7
EN_AVC
6
PON_AVC
5
4
PON_LNA
3
PON_PGAL
2
PON_ADCL
1
PON_PGAR
0
PON_ADCR
BIT
SYMBOL
DESCRIPTION
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