參數(shù)資料
型號: UDA1380
英文描述: Stereo audio coder-decoder for MD, CD and MP3
中文描述: 立體聲音頻編碼器,可用于MD,CD和MP3解碼器
文件頁數(shù): 12/68頁
文件大小: 278K
代理商: UDA1380
2002 Sep 16
12
Philips Semiconductors
Product specification
Stereo audio coder-decoder
for MD, CD and MP3
UDA1380
8.1.2
C
LOCK DISTRIBUTION
Figure 5 shows the main clock distribution for the SYSCLK domain and the WSPLL clock domain.
For power saving reasons each clock signal inside the system must be controlled and enabled via a separate bit in the
L3-bus and I
2
C-bus registers (ADC_CLK).
The DAC part of the UDA1380 can operate from 8 to 100 kHz sampling frequency (f
s
). This applies to the DAC part only;
the ADC part can run from 8 to 55 kHz.
handbook, full pagewidth
DECIMATOR
I
2
S-BUS
OUTPUT BLOCK
I
2
S-BUS
INPUT BLOCK
L3 or I
2
C-BUS
REGISTER
DECIMATOR
ADC
128fs
128fs
enable clock
256/384/512/768fs
enable
clock
ADC_CLK
CLK_DIV
SYSCLK
WSPLL
WSI
FSDAC
INTERPOLATOR
L3 or I
2
C-BUS
REGISTER
INTERPOLATOR
128fs
128fs
256fs
enable clock
MGU528
enable
clock
DAC_CLK
Fig.5 Clock routing for the main blocks inside the coder-decoder.
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